公开(公告)号：US11728395B2

公开(公告)日：2023-08-15

申请号：US17867579

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Aaron Michael Lowe

IPC: H01L29/40 ,  H01L21/28 ,  G11C11/22 ,  G11C5/06 ,  H01L29/78 ,  H01L27/06 ,  H10B12/00 ,  H10B53/00

CPC classification number: H01L29/40111 ,  G11C5/06 ,  G11C11/221 ,  G11C11/2257 ,  H01L27/0688 ,  H01L29/7827 ,  H10B12/30 ,  H10B53/00

Abstract: Some embodiments include an integrated transistor having an active region comprising semiconductor material. The active region includes a first source/drain region, a second source/drain region and a channel region between the first and second source/drain regions. A conductive gating structure is operatively proximate the channel region and comprises molybdenum. The integrated transistor may be incorporated into integrated memory, such as, for example, DRAM, FeFET memory, etc. Some embodiments include methods of forming integrated assemblies and devices, such as, for example, integrated transistors, integrated memory, etc.

公开(公告)号：US20220310637A1

公开(公告)日：2022-09-29

申请号：US17216269

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Aaron Michael Lowe ,  Zhuo Chen ,  Marko Milojevic ,  Timothy A. Quick ,  Richard J. Hill ,  Scott E. Sills

IPC: H01L27/11514 ,  H01L27/108 ,  H01L27/12 ,  H01L27/13

Abstract: Some embodiments include an integrated transistor having an active region comprising semiconductor material. A conductive gating structure is adjacent to the active region. The conductive gating structure includes an inner region proximate the active region and includes an outer region distal from the active region. The inner region includes a first material containing titanium and nitrogen, and the outer region includes a metal-containing second material. The second material has a higher conductivity than the first material. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210366525A1

公开(公告)日：2021-11-25

申请号：US17397028

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  Richard J. Hill ,  Aaron Michael Lowe

IPC: G11C7/18 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: A method used in forming a memory array comprises forming digitlines above and electrically couple to memory cells there-below. The digitlines are laterally-spaced relative one another in a vertical cross-section. An upwardly-open void-space is laterally-between immediately-adjacent of the digitlines in the vertical cross-section. Conductive material of the digitlines is covered with masking material that is in and less-than-fills the upwardly-open void-spaces. The masking material is removed from being directly above tops of the digitlines to expose the conductive digitline material and to leave the masking material over sidewalls of the conductive digitline material in the upwardly-open void-spaces. Insulative material is selectively grown from the exposed conductive digitline material relative to the masking material across the upwardly-open void-spaces to form covered void-spaces there-from between the immediately-adjacent digitlines in the vertical cross-section. Structures independent of method are disclosed.

公开(公告)号：US11735672B2

公开(公告)日：2023-08-22

申请号：US17216269

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Aaron Michael Lowe ,  Zhuo Chen ,  Marko Milojevic ,  Timothy A. Quick ,  Richard J. Hill ,  Scott E. Sills

IPC: H01L29/786 ,  H01L27/13 ,  H01L27/12 ,  H10B53/20 ,  H10B12/00

CPC classification number: H01L29/78642 ,  H01L27/1203 ,  H01L27/13 ,  H10B12/05 ,  H10B12/31 ,  H10B53/20

Abstract: Some embodiments include an integrated transistor having an active region comprising semiconductor material. A conductive gating structure is adjacent to the active region. The conductive gating structure includes an inner region proximate the active region and includes an outer region distal from the active region. The inner region includes a first material containing titanium and nitrogen, and the outer region includes a metal-containing second material. The second material has a higher conductivity than the first material. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11120852B2

公开(公告)日：2021-09-14

申请号：US16793263

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  Richard J. Hill ,  Aaron Michael Lowe

IPC: G11C7/18 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: A method used in forming a memory array comprises forming digitlines above and electrically couple to memory cells there-below. The digitlines are laterally-spaced relative one another in a vertical cross-section. An upwardly-open void-space is laterally-between immediately-adjacent of the digitlines in the vertical cross-section. Conductive material of the digitlines is covered with masking material that is in and less-than-fills the upwardly-open void-spaces. The masking material is removed from being directly above tops of the digitlines to expose the conductive digitline material and to leave the masking material over sidewalls of the conductive digitline material in the upwardly-open void-spaces. Insulative material is selectively grown from the exposed conductive digitline material relative to the masking material across the upwardly-open void-spaces to form covered void-spaces there-from between the immediately-adjacent digitlines in the vertical cross-section. Structures independent of method are disclosed.

公开(公告)号：US20240282856A1

公开(公告)日：2024-08-22

申请号：US18648180

申请日：2024-04-26

Applicant: Micron Technology, Inc.

Inventor： Yoshitaka Nakamura ,  Yi Fang Lee ,  Jerome A. Imonigie ,  Scott E. Sills ,  Aaron Michael Lowe

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/24 ,  H01L29/417 ,  H01L29/45 ,  H10B12/00

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/41741 ,  H01L29/45 ,  H10B12/05 ,  H10B12/31

Abstract: Some embodiments include an integrated assembly having an access device between a storage element and a conductive structure. The access device has channel material which includes semiconductor material. The channel material has a first end and an opposing second end, and has a side extending from the first end to the second end. The first end is adjacent the conductive structure, and the second end is adjacent the storage element. Conductive gate material is adjacent the side of the channel material. A first domed metal-containing cap is over the conductive structure and under the channel material and/or a second domed metal-containing cap is over the channel material and under the storage element. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12015080B2

公开(公告)日：2024-06-18

申请号：US16998877

申请日：2020-08-20

Applicant: Micron Technology, Inc.

Inventor： Yoshitaka Nakamura ,  Yi Fang Lee ,  Jerome A. Imonigie ,  Scott E. Sills ,  Aaron Michael Lowe

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/24 ,  H01L29/417 ,  H01L29/45 ,  H10B12/00

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/41741 ,  H01L29/45 ,  H10B12/05 ,  H10B12/31

Abstract: Some embodiments include an integrated assembly having an access device between a storage element and a conductive structure. The access device has channel material which includes semiconductor material. The channel material has a first end and an opposing second end, and has a side extending from the first end to the second end. The first end is adjacent the conductive structure, and the second end is adjacent the storage element. Conductive gate material is adjacent the side of the channel material. A first domed metal-containing cap is over the conductive structure and under the channel material and/or a second domed metal-containing cap is over the channel material and under the storage element. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11527623B2

公开(公告)日：2022-12-13

申请号：US16940852

申请日：2020-07-28

Applicant: Micron Technology, Inc.

Inventor： Aaron Michael Lowe

IPC: H01L29/40 ,  H01L21/28 ,  H01L27/11502 ,  H01L27/108 ,  G11C11/22 ,  G11C5/06 ,  H01L29/78 ,  H01L27/06

Abstract: Some embodiments include an integrated transistor having an active region comprising semiconductor material. The active region includes a first source/drain region, a second source/drain region and a channel region between the first and second source/drain regions. A conductive gating structure is operatively proximate the channel region and comprises molybdenum. The integrated transistor may be incorporated into integrated memory, such as, for example, DRAM, FeFET memory, etc. Some embodiments include methods of forming integrated assemblies and devices, such as, for example, integrated transistors, integrated memory, etc.

公开(公告)号：US20210257012A1

公开(公告)日：2021-08-19

申请号：US16793263

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  Richard J. Hill ,  Aaron Michael Lowe

IPC: G11C7/18 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556

Abstract: A method used in forming a memory array comprises forming digitlines above and electrically couple to memory cells there-below. The digitlines are laterally-spaced relative one another in a vertical cross-section. An upwardly-open void-space is laterally-between immediately-adjacent of the digitlines in the vertical cross-section. Conductive material of the digitlines is covered with masking material that is in and less-than-fills the upwardly-open void-spaces. The masking material is removed from being directly above tops of the digitlines to expose the conductive digitline material and to leave the masking material over sidewalls of the conductive digitline material in the upwardly-open void-spaces. Insulative material is selectively grown from the exposed conductive digitline material relative to the masking material across the upwardly-open void-spaces to form covered void-spaces there-from between the immediately-adjacent digitlines in the vertical cross-section. Structures independent of method are disclosed.

公开(公告)号：US11640837B2

公开(公告)日：2023-05-02

申请号：US17397028

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  Richard J. Hill ,  Aaron Michael Lowe

IPC: G11C7/18 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: A method used in forming a memory array comprises forming digitlines above and electrically couple to memory cells there-below. The digitlines are laterally-spaced relative one another in a vertical cross-section. An upwardly-open void-space is laterally-between immediately-adjacent of the digitlines in the vertical cross-section. Conductive material of the digitlines is covered with masking material that is in and less-than-fills the upwardly-open void-spaces. The masking material is removed from being directly above tops of the digitlines to expose the conductive digitline material and to leave the masking material over sidewalls of the conductive digitline material in the upwardly-open void-spaces. Insulative material is selectively grown from the exposed conductive digitline material relative to the masking material across the upwardly-open void-spaces to form covered void-spaces there-from between the immediately-adjacent digitlines in the vertical cross-section. Structures independent of method are disclosed.