公开(公告)号：US20230113573A1

公开(公告)日：2023-04-13

申请号：US18048633

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

公开(公告)号：US11990370B2

公开(公告)日：2024-05-21

申请号：US18048633

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76883 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/5283

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

公开(公告)号：US20210193493A1

公开(公告)日：2021-06-24

申请号：US16719366

申请日：2019-12-18

Applicant: Micron Technology, Inc.

Inventor： Denzil S. Frost ,  Richard T. Housley ,  David S. Pratt ,  Trupti D. Gawai

IPC: H01L21/68 ,  H01L23/544 ,  G06T7/00 ,  G06T7/73

Abstract: A method for determining overlay measurements includes orienting a wafer to align portions of lines of a pattern of an overlay mark with a direction in which a source emits light at the wafer and align other portions of the lines of the pattern to extend in a direction perpendicular to the direction in which the illumination source emits light at the wafer. The method includes capturing at least one image of the wafer via an imager sensor. The method also includes determining contrasts of regions of the overlay mark and determining a location of the overlay mark. Overlay marks include a pattern defining an array of columns. Each column includes a set of continuous lines oriented parallel to each other and extending in a first direction within a first region of a column and extending in a second different direction in a second region of the column.

公开(公告)号：US20170317028A1

公开(公告)日：2017-11-02

申请号：US15645894

申请日：2017-07-10

Applicant: Micron Technology, Inc.

Inventor： David S. Pratt

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/768 ,  H01L23/29

CPC classification number: H01L23/5384 ,  H01L21/76898 ,  H01L23/293 ,  H01L23/3157 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L24/17 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.

公开(公告)号：US08994163B2

公开(公告)日：2015-03-31

申请号：US13749521

申请日：2013-01-24

Applicant: Micron Technology, Inc.

Inventor： David S. Pratt

IPC: H01L23/02 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/14 ,  H01L23/48 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2224/81 ,  H01L2224/05552

Abstract: Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releaseably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns.

Abstract translation: 堆叠的半导体器件，半导体组件，堆叠半导体器件的制造方法以及制造半导体组件的方法。 半导体组件的一个实施例包括具有可释放地附接到临时载体，后侧和主动侧的多个第一裸片的有源侧的薄化半导体晶片。 单独的第一裸片具有集成电路，首先通过芯片互连电连接到集成电路，以及暴露在晶片背面的互连触点。 组件还包括多个分开的第二模具，其附接到正面上的对应的第一模具，其中各个第二模具具有集成电路，通过电连接到集成电路的模具互连和后侧的接触点，并且其中所述个体 第二模具具有大约小于100微米的厚度。

公开(公告)号：US20230163030A1

公开(公告)日：2023-05-25

申请号：US18151378

申请日：2023-01-06

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David A. Kewley ,  Aaron M. Lowe ,  Radhakrishna Kotti ,  David S. Pratt

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L23/535

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an insulative material at least partially over an electrically conductive feature. The method can further include forming a ring of electrically non-conductive material extending at least partially about a sidewall of the insulative material that defines the opening. The method can further include removing a portion of the ring to form an opening over the electrically conductive feature, and then depositing an electrically conductive material into the opening in the ring to form a conductive via electrically coupled to the electrically conductive feature.

公开(公告)号：US11574842B2

公开(公告)日：2023-02-07

申请号：US17230833

申请日：2021-04-14

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David A. Kewley ,  Aaron M. Lowe ,  Radhakrishna Kotti ,  David S. Pratt

IPC: H01L21/768 ,  H01L23/535

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an insulative material at least partially over an electrically conductive feature. The method can further include forming a ring of electrically non-conductive material extending at least partially about a sidewall of the insulative material that defines the opening. The method can further include removing a portion of the ring to form an opening over the electrically conductive feature, and then depositing an electrically conductive material into the opening in the ring to form a conductive via electrically coupled to the electrically conductive feature.

公开(公告)号：US10020287B2

公开(公告)日：2018-07-10

申请号：US14959500

申请日：2015-12-04

Applicant: Micron Technology, Inc.

Inventor： David S. Pratt ,  Kyle K. Kirby ,  Dewali Ray

IPC: H01L25/04 ,  H01L25/065 ,  H01L21/768 ,  H01L25/00 ,  H01L23/498 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/043 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05026 ,  H01L2224/051 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2924/01019 ,  H01L2924/00014

Abstract: Pass-through interconnect structures for microelectronic dies and associated systems and methods are disclosed herein. In one embodiment, a microelectronic die assembly includes a support substrate, a first microelectronic die positioned at least partially over the support substrate, and a second microelectronic die positioned at least partially over the first die. The first die includes a semiconductor substrate, a conductive trace extending over a portion of the semiconductor substrate, a substrate pad between the trace and the portion of the semiconductor substrate, and a through-silicon via (TSV) extending through the trace, the substrate pad, and the portion of the semiconductor substrate. The second die is electrically coupled to the support substrate via a conductive path that includes the TSV.

公开(公告)号：US20150194415A1

公开(公告)日：2015-07-09

申请号：US14665718

申请日：2015-03-23

Applicant: Micron Technology, Inc.

Inventor： David S. Pratt

IPC: H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L21/304 ,  H01L21/78 ,  H01L21/66

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/14 ,  H01L23/48 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2224/81 ,  H01L2224/05552

Abstract: Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releaseably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns.

Abstract translation: 堆叠的半导体器件，半导体组件，堆叠半导体器件的制造方法以及制造半导体组件的方法。 半导体组件的一个实施例包括具有可释放地附接到临时载体，后侧和主动侧的多个第一裸片的有源侧的薄化半导体晶片。 单独的第一裸片具有集成电路，首先通过芯片互连电连接到集成电路，以及暴露在晶片背面的互连触点。 组件还包括多个分开的第二模具，其附接到正面上的对应的第一模具，其中各个第二模具具有集成电路，通过电连接到集成电路的模具互连和后侧的接触点，并且其中所述个体 第二模具具有大约小于100微米的厚度。

公开(公告)号：US20130134605A1

公开(公告)日：2013-05-30

申请号：US13749521

申请日：2013-01-24

Applicant: Micron Technology, Inc.

Inventor： David S. Pratt

IPC: H01L23/48

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/14 ,  H01L23/48 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2224/81 ,  H01L2224/05552

Abstract: Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releaseably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns.