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公开(公告)号：US10796778B2
公开(公告)日：2020-10-06
申请号：US16694043
申请日：2019-11-25
Applicant: Micron Technology, Inc.
Inventor： Han Zhao , Akira Goda , Krishna K. Parat , Aurelio Giancarlo Mauri , Haitao Liu , Toru Tanzawa , Shigekazu Yamada , Koji Sakui
Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.
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公开(公告)号：US20200265895A1
公开(公告)日：2020-08-20
申请号：US16868777
申请日：2020-05-07
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Toru Tanzawa , Han Zhao
Abstract: Methods of operating a memory include activating a respective memory cell of each string of series-connected memory cells of a plurality of strings of series-connected memory cells, selectively activating a target memory cell of a selected string of series-connected memory cells of the plurality of strings of series-connected memory cells depending upon its data state, and deactivating a respective memory cell of each string of series-connected memory cells of a first subset of the plurality of strings of series-connected memory cells.
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公开(公告)号：US20190013077A1
公开(公告)日：2019-01-10
申请号：US16127469
申请日：2018-09-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Toru Tanzawa , Han Zhao
CPC classification number: G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26
Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of series-connected memory cells of the plurality of strings of series-connected memory cells may be selectively connected to a common data line through a corresponding respective select gate, a first set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a second set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of only a portion of the plurality of strings of series-connected memory cells.
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公开(公告)号：US09881686B2
公开(公告)日：2018-01-30
申请号：US15393719
申请日：2016-12-29
Applicant: Micron Technology, Inc.
Inventor： Han Zhao , Akira Goda , Krishna K. Parat , Aurelio Giancarlo Mauri , Haitao Liu , Toru Tanzawa , Shigekazu Yamada , Koji Sakui
CPC classification number: G11C16/3459 , G11C8/08 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/32 , G11C16/3445 , G11C2213/71
Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.
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公开(公告)号：US20170110198A1
公开(公告)日：2017-04-20
申请号：US15393719
申请日：2016-12-29
Applicant: Micron Technology, Inc.
Inventor： Han Zhao , Akira Goda , Krishna K. Parat , Aurelio Giancarlo Mauri , Haitao Liu , Toru Tanzawa , Shigekazu Yamada , Koji Sakui
CPC classification number: G11C16/3459 , G11C8/08 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/32 , G11C16/3445 , G11C2213/71
Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.
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Patent Agency Ranking
公开(公告)号：US11721396B2
公开(公告)日：2023-08-08
申请号：US17012442
申请日：2020-09-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Purval S. Sule , Han Liu , Andrea D'Alessandro , Pranav Kalavade , Han Zhao , Shantanu Rajwade
IPC: G11C16/12 , G11C11/4074 , G11C16/04 , G11C16/34 , G11C5/06
CPC classification number: G11C16/12 , G11C5/063 , G11C11/4074 , G11C16/0483 , G11C16/3427
Abstract: Memories having a controller configured to perform methods during programming operations including apply a first voltage level to a data line selectively connected to a selected memory cell selected, apply a lower second voltage level to a select gate connected between the data line and the memory cell, decrease the voltage level applied to the data line from the first voltage level to a third voltage level while continuing to apply the second voltage level to the select gate, increase the voltage level applied to the select gate from the second voltage level to a fourth voltage level after the voltage level of the data line settles to the third voltage level, and apply a programming voltage to the memory cell after increasing the voltage level applied to the select gate to the fourth voltage level.
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公开(公告)号：US10482974B1
公开(公告)日：2019-11-19
申请号：US16106185
申请日：2018-08-21
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Violante Moschiano , Purval S. Sule , Han Liu , Andrea D'Alessandro , Pranav Kalavade , Han Zhao , Shantanu Rajwade
Abstract: Methods include applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.
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8.发明申请公开(公告)号：US20150287472A1
公开(公告)日：2015-10-08
申请号：US14746416
申请日：2015-06-22
Applicant: Micron Technology, Inc.
Inventor： Han Zhao , Akira Goda , Krishna K. Parat , Aurelio Giancarlo Mauri , Haitao Liu , Toru Tanzawa , Shigekazu Yamada , Koji Sakui
CPC classification number: G11C16/3459 , G11C8/08 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/32 , G11C16/3445 , G11C2213/71
Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.
Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。 描述其他实施例。
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9.发明申请公开(公告)号：US20200234781A1
公开(公告)日：2020-07-23
申请号：US16694043
申请日：2019-11-25
Applicant: Micron Technology, Inc.
Inventor： Han Zhao , Akira Goda , Krishna K. Parat , Aurelio Giancarlo Mauri , Haitao Liu , Toru Tanzawa , Shigekazu Yamada , Koji Sakui
Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.
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公开(公告)号：US10672477B2
公开(公告)日：2020-06-02
申请号：US16127469
申请日：2018-09-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Toru Tanzawa , Han Zhao
Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of series-connected memory cells of the plurality of strings of series-connected memory cells may be selectively connected to a common data line through a corresponding respective select gate, a first set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a second set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of only a portion of the plurality of strings of series-connected memory cells.
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