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    Program operations in memory
    4.
    发明授权
    Program operations in memory 有权

    公开(公告)号：US10600456B2

    公开(公告)日：2020-03-24

    申请号：US16215693

    申请日：2018-12-11

    Applicant: Micron Technology, Inc.

    Inventor： Marco Sforzin ,  Paolo Amato ,  Innocenzo Tortorelli ,  Marco Dallabora

    IPC: G11C11/00 ,  G11C7/10 ,  G11C13/00

    Abstract: The present disclosure includes apparatuses and methods related to program operations in memory. An example apparatus can perform a program operation on an array of memory cells by applying a first program signal to a first portion of the array of memory cells that are to remain in a first state in response to the program operation, wherein the first program signal programs memory cells to a second state and then to the first state.

    Memory management
    5.
    发明授权
    Memory management 有权

    公开(公告)号：US10261876B2

    公开(公告)日：2019-04-16

    申请号：US15345862

    申请日：2016-11-08

    Applicant: Micron Technology, Inc.

    Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

    IPC: G06F11/20 ,  G06F3/06

    Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.

    Program operations in memory
    6.
    发明授权
    Program operations in memory 有权

    公开(公告)号：US10157650B1

    公开(公告)日：2018-12-18

    申请号：US15659728

    申请日：2017-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Marco Sforzin ,  Paolo Amato ,  Innocenzo Tortorelli ,  Marco Dallabora

    IPC: G11C5/02 ,  G11C7/10

    Abstract: The present disclosure includes apparatuses and methods related to program operations in memory. An example apparatus can perform a program operation on an array of memory cells by applying a first program signal to a first portion of the array of memory cells that are to remain in a first state in response to the program operation, wherein the first program signal programs memory cells to a second state and then to the first state.

    DATA STATE SYNCHRONIZATION
    7.
    发明申请
    DATA STATE SYNCHRONIZATION 有权

    公开(公告)号：US20210166775A1

    公开(公告)日：2021-06-03

    申请号：US17170386

    申请日：2021-02-08

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Amato ,  Marco Dallabora ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

    IPC: G11C29/42 ,  G11C29/44 ,  G11C13/00 ,  G11C7/22 ,  G06F11/10

    Abstract: An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.

    DEDICATED COMMANDS FOR MEMORY OPERATIONS
    9.
    发明申请
    DEDICATED COMMANDS FOR MEMORY OPERATIONS 审中-公开

    公开(公告)号：US20200082883A1

    公开(公告)日：2020-03-12

    申请号：US16128550

    申请日：2018-09-12

    Applicant: Micron Technology, Inc.

    Inventor： Daniele Balluchi ,  Paolo Amato ,  Graziano Mirichigni ,  Danilo Caraccio ,  Marco Sforzin ,  Marco Dallabora

    IPC: G11C13/00 ,  G11C8/12

    Abstract: An apparatus can have a memory comprising an array of resistance variable memory cells and a controller. The controller can be configured to receive to a dedicated command to write all cells in a number of groups of the resistance variable memory cells to a first state without transferring any host data corresponding to the first state to the number of groups. The controller can be configured to, in response to the dedicated command, perform a read operation on each respective group to determine states of the cells in each respective group, determine from the read operation any cells in each respective group programmed to a second state, and write only the cells determined to be in the second state to the first state.

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