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    Memory Array And Method Used In Forming A Memory Array
    1.
    发明申请
    Memory Array And Method Used In Forming A Memory Array 有权

    公开(公告)号：US20250024675A1

    公开(公告)日：2025-01-16

    申请号：US18904472

    申请日：2024-10-02

    Applicant: Micron Technology, Inc.

    Inventor： Sidhartha Gupta ,  Naveen Kaushik ,  Pankaj Sharma

    IPC: H10B41/27 ,  H01L23/538 ,  H10B43/27

    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually electrically coupled to individual of the channel-material strings. Insulating material is laterally-between immediately-adjacent of the conductive vias. At least some of the insulating material is vertically removed to form an upwardly-open void-space that is circumferentially about multiple of the conductive vias. Insulative material formed laterally-between the immediately-adjacent conductive vias to form a covered void-space from the upwardly-open void-space. Digitlines are formed above that are individually electrically coupled to a plurality of individual of the conductive vias there-below. Other embodiments, including structure independent of method, are disclosed.

    2-TRANSISTOR MEMORY CELL AND GATE STRUCTURE HAVING MULTIPLE PORTIONS
    2.
    发明公开
    2-TRANSISTOR MEMORY CELL AND GATE STRUCTURE HAVING MULTIPLE PORTIONS 审中-公开

    公开(公告)号：US20240268091A1

    公开(公告)日：2024-08-08

    申请号：US18432870

    申请日：2024-02-05

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Pankaj Sharma ,  Manuj Nahar ,  Nicholas R. Tapias ,  Scott E. Sills

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first conductive region; a second conductive region; a memory cell between the first and second conductive regions and including a first transistor including a first region coupled to the first and second conductive regions, and a charge storage structure separated from the first conduction region, and a second transistor including a second region coupled to the charge storage structure and the second conductive region; and a structure separated from the first region, the charge storage structure, and the second region by a dielectric structure, the structure forming part of a gate of the first transistor and the second transistor, and the structure including a first portion adjacent the dielectric structure, and a second portion adjacent the first portion, wherein the first portion includes a semiconductor material and the second portion includes a conductive material.

    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SEPARATE READ AND WRITE DATA LINES
    3.
    发明公开
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SEPARATE READ AND WRITE DATA LINES 审中-公开

    公开(公告)号：US20240074138A1

    公开(公告)日：2024-02-29

    申请号：US18238269

    申请日：2023-08-25

    Applicant: Micron Technology, Inc.

    Inventor： Durai Vishak Nirmal Ramaswamy ,  Karthik Sarpatwari ,  Kamal M. Karda ,  Pankaj Sharma

    IPC: H10B12/00

    CPC classification number: H10B12/00

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line; a second data line adjacent the first data line and separated from the first data line by a first dielectric structure; and a memory cell formed over the first and second data lines. The memory cell includes a first transistor including a first channel region formed over and coupled to the first data line, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over and coupled to the second data line, wherein the charge storage structure is formed over and coupled to the second channel region; and a second dielectric structure between the first channel region and each of the second channel region and the charge storage structure.

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    5.
    发明申请
    Integrated Assemblies and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20220238546A1

    公开(公告)日：2022-07-28

    申请号：US17158259

    申请日：2021-01-26

    Applicant: Micron Technology, Inc.

    Inventor： Sidhartha Gupta ,  Naveen Kaushik ,  Pankaj Sharma ,  Kyle A. Ritter

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

    Abstract: Some embodiments include an integrated assembly having a channel-material-pillar extending vertically through a stack of alternating conductive levels and insulative levels. The channel-material-pillar includes a first semiconductor material. A second semiconductor material is directly against an upper region of the channel-material-pillar. The second semiconductor material has a higher dopant concentration than the first semiconductor material and joins to the first semiconductor along an abrupt interfacial region such that there is little to no mixing of dopant from the second semiconductor material into the first semiconductor material. Some embodiments include methods of forming integrated assemblies.

    Integrated Memory having Non-Ohmic Devices and Capacitors
    6.
    发明申请
    Integrated Memory having Non-Ohmic Devices and Capacitors 有权

    公开(公告)号：US20210193663A1

    公开(公告)日：2021-06-24

    申请号：US16721006

    申请日：2019-12-19

    Applicant: Micron Technology, Inc.

    Inventor： Pankaj Sharma ,  Muralikrishnan Balakrishnan

    IPC: H01L27/108 ,  H01L27/11502 ,  H01L45/00 ,  H01L49/00 ,  H01L29/786 ,  G11C11/22

    Abstract: Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.

    Apparatuses including device structures including pillar structures
    7.
    发明授权
    Apparatuses including device structures including pillar structures 有权

    公开(公告)号：US12154853B2

    公开(公告)日：2024-11-26

    申请号：US18164903

    申请日：2023-02-06

    Applicant: Micron Technology, Inc.

    Inventor： Naveen Kaushik ,  Sidhartha Gupta ,  Pankaj Sharma ,  Haitao Liu

    IPC: H01L23/522 ,  G11C5/06 ,  H01L21/48 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

    Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.

    Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems
    9.
    发明授权
    Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems 有权

    公开(公告)号：US11605589B2

    公开(公告)日：2023-03-14

    申请号：US17161313

    申请日：2021-01-28

    Applicant: Micron Technology, Inc.

    Inventor： Naveen Kaushik ,  Sidhartha Gupta ,  Pankaj Sharma ,  Haitao Liu

    IPC: H01L23/522 ,  H01L27/11582 ,  G11C5/06 ,  H01L21/48 ,  H01L21/768 ,  H01L27/11556

    Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.

    Memory Array And Method Used In Forming A Memory Array
    10.
    发明申请
    Memory Array And Method Used In Forming A Memory Array 有权

    公开(公告)号：US20230039621A1

    公开(公告)日：2023-02-09

    申请号：US17395211

    申请日：2021-08-05

    Applicant: Micron Technology, Inc.

    Inventor： Sidhartha Gupta ,  Naveen Kaushik ,  Pankaj Sharma

    IPC: H01L27/11556 ,  H01L23/538 ,  H01L27/11582

    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually electrically coupled to individual of the channel-material strings. Insulating material is laterally-between immediately-adjacent of the conductive vias. At least some of the insulating material is vertically removed to form an upwardly-open void-space that is circumferentially about multiple of the conductive vias. Insulative material is formed laterally-between the immediately-adjacent conductive vias to form a covered void-space from the upwardly-open void-space. Digitlines are formed above that are individually electrically coupled to a plurality of individual of the conductive vias there-below. Other embodiments, including structure independent of method, are disclosed.

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