公开(公告)号：US12150289B2

公开(公告)日：2024-11-19

申请号：US17203236

申请日：2021-03-16

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Kyuseok Lee ,  Sangmin Hwang

IPC: H10B12/00 ,  G11C5/06 ,  H01L21/768

Abstract: A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20240079474A1

公开(公告)日：2024-03-07

申请号：US17903414

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Kyuseok Lee ,  Sangmin Hwang ,  Byung Yoon Kim

IPC: H01L29/66 ,  H01L29/739

CPC classification number: H01L29/66348 ,  H01L29/7395

Abstract: Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include transistors formed from a plurality of semiconductor fins, and using a number of conductive lines passing through trenches between the fins to serve as a gate for the transistor.

公开(公告)号：US11877445B2

公开(公告)日：2024-01-16

申请号：US17150020

申请日：2021-01-15

Applicant: Micron Technology, Inc.

Inventor： Sangmin Hwang ,  Kyuseok Lee ,  Christopher G. Wieduwilt

IPC: H10N70/20 ,  H10B12/00 ,  H01L27/092 ,  H01L29/78 ,  G11C11/4091 ,  G11C11/408 ,  G11C5/06

CPC classification number: H10B12/50 ,  G11C5/063 ,  G11C11/4085 ,  G11C11/4091 ,  H01L27/0924 ,  H01L29/785 ,  H10B12/36

Abstract: Some embodiments include an integrated assembly having a CMOS region. Fins extend across the CMOS region and are on a first pitch. A circuit arrangement is associated with the CMOS region and includes segments of one or more of the fins. The circuit arrangement has a first dimension along a first direction. A second region is proximate the CMOS region. Conductive structures are associated with the second region. The conductive structures extend along a second direction different than the first direction. Some of the conductive structures are electrically coupled with the circuit arrangement. The conductive structures are on a second pitch different from the first pitch. A second dimension is a distance across said some of the conductive structures along the first direction, and the second dimension is substantially the same as the first dimension.

公开(公告)号：US11450375B2

公开(公告)日：2022-09-20

申请号：US17006730

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： Takefumi Shirako ,  Masahiro Yokomichi ,  Kyuseok Lee ,  Sangmin Hwang

IPC: G11C8/08 ,  G11C11/408 ,  G11C11/16 ,  G11C8/14 ,  G11C5/14

Abstract: In some examples, a subword driver block of a memory device includes a plurality of active regions of a first type and a plurality of active regions of a second type adjacent to the plurality of active regions of the first type. The subword driver block further includes a plurality of first gate electrodes overlapping with the plurality of active regions of the first type to form a plurality of first transistors, and a plurality of second gate electrodes overlapping with the plurality of active regions of the first type to form a plurality of second transistors. Each of the second transistors is shared by a first subword driver and a second subword driver. Each of the second transistors may include a drain and a source respectively coupled to a first and second word line, which are driven by the first subword driver and the second subword driver, respectively.

公开(公告)号：US20210202491A1

公开(公告)日：2021-07-01

申请号：US17203236

申请日：2021-03-16

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Kyuseok Lee ,  Sangmin Hwang

IPC: H01L27/108 ,  G11C5/06 ,  H01L21/768

Abstract: A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20190259444A1

公开(公告)日：2019-08-22

申请号：US16234319

申请日：2018-12-27

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Sangmin Hwang ,  Si-Woo Lee

IPC: G11C11/4091 ,  G11C11/22 ,  G11C11/4097

Abstract: Some embodiments include an apparatus having first and second comparative bitlines extending horizontally and coupled with a sense amplifier. First memory cell structures are coupled with the first comparative bitline. Each of the first memory cell structures has a first transistor associated with a first capacitor. Second memory cell structures are coupled with the second comparative bitline. Each of the second memory cell structures has a second transistor associated with a second capacitor. Each of the first capacitors has a container-shaped first node and is vertically offset from an associated first sister capacitor which is a mirror image of its associated first capacitor along a horizontal plane. Each of the second capacitors has a container-shaped first node and is vertically offset from an associated second sister capacitor which is a mirror image of its associated second capacitor along the horizontal plane.

公开(公告)号：US20240292607A1

公开(公告)日：2024-08-29

申请号：US18583319

申请日：2024-02-21

Applicant: Micron Technology, Inc.

Inventor： Jun Ho Lee ,  Byung Yoon Kim ,  Sangmin Hwang

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/02

Abstract: A variety of applications can include an apparatus having a device including line contacts to closely-spaced conductive signal lines structured such that a sufficient margin for shorts between a signal line and a line contact to a directly adjacent signal line is maintained even with a misalignment of the line contact. In an embodiment, formation of a memory device can include forming a line contact on and contacting an access line for an array of memory cells, using a two stage removal procedure of different removal processes. The two stage removal procedure can include removing a portion of processing layers above an insulating protective layer positioned on the access line and selectively removing the insulating protective layer, exposing a portion of the access line, without removing material of the access line. The line contact can be formed on and contacting the top exposed portion of the access line.

公开(公告)号：US20240114680A1

公开(公告)日：2024-04-04

申请号：US18533410

申请日：2023-12-08

Applicant: Micron Technology, Inc.

Inventor： Sangmin Hwang ,  Kyuseok Lee ,  Christopher G. Wieduwilt

IPC: H10B12/00 ,  G11C5/06 ,  G11C11/408 ,  G11C11/4091 ,  H01L27/092 ,  H01L29/78

CPC classification number: H10B12/50 ,  G11C5/063 ,  G11C11/4085 ,  G11C11/4091 ,  H01L27/0924 ,  H01L29/785 ,  H10B12/36

Abstract: Some embodiments include an integrated assembly having a CMOS region. Fins extend across the CMOS region and are on a first pitch. A circuit arrangement is associated with the CMOS region and includes segments of one or more of the fins. The circuit arrangement has a first dimension along a first direction. A second region is proximate the CMOS region. Conductive structures are associated with the second region. The conductive structures extend along a second direction different than the first direction. Some of the conductive structures are electrically coupled with the circuit arrangement. The conductive structures are on a second pitch different from the first pitch. A second dimension is a distance across said some of the conductive structures along the first direction, and the second dimension is substantially the same as the first dimension.

公开(公告)号：US20220320103A1

公开(公告)日：2022-10-06

申请号：US17843662

申请日：2022-06-17

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Sangmin Hwang

IPC: H01L27/108 ,  H01L27/06 ,  G11C11/402 ,  H01L25/065

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and vertically oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.

公开(公告)号：US20220285365A1

公开(公告)日：2022-09-08

申请号：US17189485

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sangmin Hwang ,  Kyuseok Lee

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.