公开(公告)号：US20240332002A1

公开(公告)日：2024-10-03

申请号：US18743882

申请日：2024-06-14

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar ,  Farrell M. Good

IPC: H01L21/02 ,  C01B32/00 ,  C01B33/00 ,  C23C16/04 ,  C23C16/452

CPC classification number: H01L21/02167 ,  C01B32/00 ,  C01B33/00 ,  C23C16/045 ,  C23C16/452 ,  H01L21/02274 ,  H01L21/02381 ,  H01L2221/1047

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and one or more silicon carbide materials adjacent to the one or more stacks of materials. The materials of the one or more stacks comprise a single chalcogenide material and one or more of a conductive carbon material, a conductive material, and a hardmask material. The one or more silicon carbide materials comprises silicon carbide, silicon carboxide, silicon carbonitride, silicon carboxynitride, and also comprise silicon-carbon covalent bonds. The one or more silicon carbide materials is configured as a liner or as a seal. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

公开(公告)号：US20220376176A1

公开(公告)日：2022-11-24

申请号：US17818313

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar ,  Robert K. Grubbs ,  Farrell M. Good ,  Adam W. Saxler ,  Andrea Gotti

IPC: H01L45/00 ,  H01L27/24

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

公开(公告)号：US11444243B2

公开(公告)日：2022-09-13

申请号：US16665679

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar ,  Robert K. Grubbs ,  Farrell M. Good ,  Adam W. Saxler ,  Andrea Gotti

IPC: H01L45/00

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

公开(公告)号：US20210359089A1

公开(公告)日：2021-11-18

申请号：US15930090

申请日：2020-05-12

Applicant: Micron Technology, Inc.

Inventor： Ahmed Nayaz Noemaun ,  Stephen W. Russell ,  Tao D. Nguyen ,  Santanu Sarkar

IPC: H01L29/40 ,  H01L21/82 ,  H01L29/66

Abstract: Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.

公开(公告)号：US20240250132A1

公开(公告)日：2024-07-25

申请号：US18594397

申请日：2024-03-04

Applicant: Micron Technology, Inc.

Inventor： Ahmed Nayaz Noemaun ,  Stephen W. Russell ,  Tao D. Nguyen ,  Santanu Sarkar

IPC: H01L29/40 ,  H01L21/82 ,  H01L29/66

CPC classification number: H01L29/408 ,  H01L21/82 ,  H01L29/6656

Abstract: Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.

公开(公告)号：US11948984B2

公开(公告)日：2024-04-02

申请号：US18099972

申请日：2023-01-23

Applicant: Micron Technology, Inc.

Inventor： Ahmed Nayaz Noemaun ,  Stephen W. Russell ,  Tao D. Nguyen ,  Santanu Sarkar

IPC: H01L29/40 ,  H01L21/82 ,  H01L29/66

CPC classification number: H01L29/408 ,  H01L21/82 ,  H01L29/6656

Abstract: Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.

公开(公告)号：US20220263023A1

公开(公告)日：2022-08-18

申请号：US17178086

申请日：2021-02-17

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar

IPC: H01L45/00 ,  H01L21/687 ,  H01L21/02 ,  H01L27/24 ,  C23C16/458 ,  C23C16/46 ,  C23C16/455 ,  C23C16/40

Abstract: Apparatus and methods related to forming films on sidewalls of memory cell stacks in memory and logic devices. In one approach, a silicon wafer is held in a chamber of an atomic layer deposition (ALD) reactor. A temperature in the reactor is controlled to a first temperature (e.g., room temperature or below) where a first gas reactant that is provided into the chamber condenses and is adsorbed on the target wafer or substrate. The first reactant or precursor is partly vaporized at a second temperature in the reactor that is greater than the first temperature. A second gas reactant is provided into the chamber. The second gas reactant reacts with the adsorbed portion of the first gas reactant in its activated state. The reaction product is a film on the sidewall of a memory cell stack or logic devices. The foregoing steps are repeated to form a desired thickness of the film.

公开(公告)号：US11682623B2

公开(公告)日：2023-06-20

申请号：US17375345

申请日：2021-07-14

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar

IPC: H01L23/532 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L23/53276 ,  H01L23/5329 ,  H01L23/53261 ,  H01L29/1606 ,  H01L29/66015

Abstract: Some embodiments include an integrated assembly having a first graphene-containing-material offset from a second graphene-containing-material. The first graphene-containing-material includes a first graphene-layer-stack with first metal interspersed therein. The second graphene-containing-material includes a second graphene-layer-stack with second metal interspersed therein. A conductive interconnect couples the first and second graphene-containing materials to one another.

公开(公告)号：US20230154989A1

公开(公告)日：2023-05-18

申请号：US18099972

申请日：2023-01-23

Applicant: Micron Technology, Inc.

Inventor： Ahmed Nayaz Noemaun ,  Stephen W. Russell ,  Tao D. Nguyen ,  Santanu Sarkar

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/82

CPC classification number: H01L29/408 ,  H01L29/6656 ,  H01L21/82

Abstract: Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.

公开(公告)号：US20210233768A1

公开(公告)日：2021-07-29

申请号：US16751049

申请日：2020-01-23

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar ,  Farrell M. Good

IPC: H01L21/02 ,  C23C16/04 ,  C23C16/452

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and one or more silicon carbide materials adjacent to the one or more stacks of materials. The materials of the one or more stacks comprise a single chalcogenide material and one or more of a conductive carbon material, a conductive material, and a hardmask material. The one or more silicon carbide materials comprises silicon carbide, silicon carboxide, silicon carbonitride, silicon carboxynitride, and also comprise silicon-carbon covalent bonds. The one or more silicon carbide materials is configured as a liner or as a seal. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.