公开(公告)号：US20230391805A1

公开(公告)日：2023-12-07

申请号：US18327840

申请日：2023-06-01

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Sumeet C. Pandey ,  Stefan Uhlenbrock ,  John A. Smythe

IPC: C07F7/30 ,  C23C16/455 ,  C23C16/18

CPC classification number: C07F7/30 ,  C23C16/45553 ,  C23C16/18 ,  H01L21/02532

Abstract: A germanium precursor comprising a chemical formula of Ge(R1NC(R3)NR2)(R4) where each of R1, R2, R3, and R4 is independently selected from the group consisting of hydrogen, an alkyl, a substituted alkyl, an alkoxide, a substituted amide, an amine, a substituted amine, and a halogen. Methods of forming the germanium precursor and a precursor composition including the germanium precursor are also disclosed.

公开(公告)号：US20230317798A1

公开(公告)日：2023-10-05

申请号：US17712294

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Adharsh Rajagopal ,  Scott E. Sills ,  Sumeet C. Pandey ,  David M. Guzman

IPC: H01L29/24 ,  H01L27/108 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/24 ,  H01L27/108 ,  H01L29/7869 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02631 ,  H01L29/66969

Abstract: Systems, methods and apparatus are provided for transistors having a first source/drain region, a second source/drain region, and a channel region, wherein the channel region comprises an antimony-gallium-zinc-oxide (SbGZO) material.

公开(公告)号：US20220238340A1

公开(公告)日：2022-07-28

申请号：US17653790

申请日：2022-03-07

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Marko Milojevic ,  John A. Smythe ,  Timothy A. Quick ,  Sumeet C. Pandey

IPC: H01L21/28 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

Abstract: A method of forming a structure comprises forming a pattern of elongate features extending vertically from a base structure. Conductive material is formed on the elongate features. After completing the forming of the pattern of elongate features, the elongate features, the conductive material, or both is (are) exposed to at least one surface treatment gas. The at least one surface treatment gas comprises at least one species formulated to diminish attractive or cohesive forces at a surface of the conductive material. Apparatus and additional methods are also described.

公开(公告)号：US11270909B2

公开(公告)日：2022-03-08

申请号：US16773636

申请日：2020-01-27

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Marko Milojevic ,  John A. Smythe ,  Timothy A. Quick ,  Sumeet C. Pandey

IPC: H01L21/768 ,  H01L21/67 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538

Abstract: A method of forming a structure comprises forming a pattern of elongate features extending vertically from a base structure. Conductive material is formed on the elongate features. After completing the forming of the pattern of elongate features, the elongate features, the conductive material, or both is (are) exposed to at least one surface treatment gas. The at least one surface treatment gas comprises at least one species formulated to diminish attractive or cohesive forces at a surface of the conductive material. Apparatus and additional methods are also described.

公开(公告)号：US20210233810A1

公开(公告)日：2021-07-29

申请号：US16773636

申请日：2020-01-27

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Marko Milojevic ,  John A. Smythe ,  Timothy A. Quick ,  Sumeet C. Pandey

IPC: H01L21/768 ,  H01L21/67

Abstract: A method of forming a structure comprises forming a pattern of elongate features extending vertically from a base structure. Conductive material is formed on the elongate features. After completing the forming of the pattern of elongate features, the elongate features, the conductive material, or both is (are) exposed to at least one surface treatment gas. The at least one surface treatment gas comprises at least one species formulated to diminish attractive or cohesive forces at a surface of the conductive material. Apparatus and additional methods are also described.

公开(公告)号：US10964532B2

公开(公告)日：2021-03-30

申请号：US15857920

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Sumeet C. Pandey ,  Brenda D. Kraus ,  Stefan Uhlenbrock ,  John A. Smythe ,  Timothy A. Quick

IPC: H01L21/02

Abstract: Methods of forming silicon nitride. Silicon nitride is formed on a substrate by atomic layer deposition at a temperature of less than or equal to about 275° C. The as-formed silicon nitride is exposed to a plasma. The silicon nitride may be formed as a portion of silicon nitride and at least one other portion of silicon nitride. The portion of silicon nitride and the at least one other portion of silicon nitride may be exposed to a plasma treatment. Methods of forming a semiconductor structure are also disclosed, as are semiconductor structures and silicon precursors.

公开(公告)号：US20180226570A1

公开(公告)日：2018-08-09

申请号：US15939939

申请日：2018-03-29

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Sumeet C. Pandey

IPC: H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L43/08 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous region is proximate to the magnetic region and is formed from a precursor trap material comprising at least one attracter species having at least one trap site and a chemical affinity for the diffusive species. The diffusive species is transferred from the precursor magnetic material to the precursor trap material where it bonds to the at least one attracter species at the trap sites. The species of the enriched trap material may intermix such that the enriched trap material becomes or stays amorphous. The depleted magnetic material may then be crystallized through propagation from a neighboring crystalline material without interference from the amorphous, enriched trap material. This enables high tunnel magnetoresistance and high magnetic anisotropy strength. Methods of fabrication and semiconductor devices are also disclosed.

公开(公告)号：US20170323927A1

公开(公告)日：2017-11-09

申请号：US15660417

申请日：2017-07-26

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Sumeet C. Pandey

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  H01L43/10

CPC classification number: H01L27/222 ,  H01L27/226 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic cell includes magnetic, secondary oxide, and getter seed regions. During formation, a diffusive species is transferred from a precursor magnetic material to the getter seed region, due to a chemical affinity elicited by a getter species. The depletion of the magnetic material enables crystallization of the depleted magnetic material through crystal structure propagation from a neighboring crystalline material, without interference from the now-enriched getter seed region. This promotes high tunnel magnetoresistance and high magnetic anisotropy strength. Also during formation, another diffusive species is transferred from a precursor oxide material to the getter seed region, due to a chemical affinity elicited by another getter species. The depletion of the oxide material enables lower electrical resistance and low damping in the cell structure. Methods of fabrication and semiconductor devices are also disclosed.

公开(公告)号：US09515261B2

公开(公告)日：2016-12-06

申请号：US15080802

申请日：2016-03-25

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Sumeet C. Pandey

IPC: H01L21/3205 ,  H01L43/08 ,  G11C11/56 ,  H01L45/00

CPC classification number: H01L45/1608 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a transitory structure which alters resistance through the memory cell. The data storage region includes two or more portions, with one of the portions supporting a higher resistance segment of the transitory structure than another of the portions. Some embodiments include a method of forming a memory cell. First oxide and second oxide regions are formed between a pair of conductive structures. The oxide regions are configured to support a transitory structure which alters resistance through the memory cell. The oxide regions are different from one another so that one of the oxide regions supports a higher resistance segment of the transitory structure than the other.

Abstract translation: 一些实施例包括具有在一对导电结构之间的数据存储区域的存储单元。 数据存储区域被配置为支持通过存储器单元改变电阻的暂态结构。 数据存储区域包括两个或多个部分，其中一个部分支持短暂结构的较高电阻段，而不是另一部分。 一些实施例包括形成存储器单元的方法。 在一对导电结构之间形成第一氧化物和第二氧化物区域。 氧化物区域被配置为支持通过存储器单元改变电阻的暂态结构。 氧化物区域彼此不同，使得氧化物区域中的一个区域支持短暂结构的较高电阻段。

公开(公告)号：US20160211448A1

公开(公告)日：2016-07-21

申请号：US15080802

申请日：2016-03-25

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Sumeet C. Pandey

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a transitory structure which alters resistance through the memory cell. The data storage region includes two or more portions, with one of the portions supporting a higher resistance segment of the transitory structure than another of the portions. Some embodiments include a method of forming a memory cell. First oxide and second oxide regions are formed between a pair of conductive structures. The oxide regions are configured to support a transitory structure which alters resistance through the memory cell. The oxide regions are different from one another so that one of the oxide regions supports a higher resistance segment of the transitory structure than the other.

Abstract translation: 一些实施例包括具有在一对导电结构之间的数据存储区域的存储单元。 数据存储区域被配置为支持通过存储器单元改变电阻的暂态结构。 数据存储区域包括两个或多个部分，其中一个部分支持短暂结构的较高电阻段，而不是另一部分。 一些实施例包括形成存储器单元的方法。 在一对导电结构之间形成第一氧化物和第二氧化物区域。 氧化物区域被配置为支持通过存储器单元改变电阻的暂态结构。 氧化物区域彼此不同，使得氧化物区域中的一个区域支持短暂结构的较高电阻段。