公开(公告)号：US20250104794A1

公开(公告)日：2025-03-27

申请号：US18975645

申请日：2024-12-10

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz ,  Yoav Weinberg

IPC: G11C29/50 ,  G11C29/02

Abstract: An example method for scan-based voltage frequency scaling can include performing a plurality of at-speed scan operation on a system on chip (SoC) at a plurality of respective voltage values. The example method can include entering data gathered from at least one of the plurality of at-speed scan operations into a database. The entered data is associated with the respective plurality of voltage value. The example method can include determining a particular voltage value of the respective plurality of voltage values at which a parameter of the SoC reaches a threshold. The example method can include indicating the determined particular voltage in the database. The indicated determined particular voltage in the database can be used for performing one or more operations using the SoC.

公开(公告)号：US12182046B2

公开(公告)日：2024-12-31

申请号：US18119578

申请日：2023-03-09

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Leonid Minz ,  Yoav Weinberg ,  Ali Feiz Zarrin Ghalam ,  Luigi Pilolli

IPC: G06F13/30 ,  G06F13/16

Abstract: Operations include monitoring a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal, determining whether a period of time during which the logical level of the first pin is held at a first logical level satisfies a threshold condition, in response to determining that the period of time satisfies the threshold condition, continuing to monitor the logical level of the first pin, determining whether the logical level of the first pin changed from the first logical level to a second logical level, and in response to determining that the logical level of the first pin changed from the first logical to the second logical level, causing warmup cycles to be performed.

公开(公告)号：US20240338146A1

公开(公告)日：2024-10-10

申请号：US18743629

申请日：2024-06-14

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Mustafa N. Kaynak ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory device having a bit-flipping decoder. The decoder having a plurality of circuits operatable to perform parallel computation to decode a codeword according to a plurality of columns of a parity matrix. The decoder is configured to provide columns of the parity matrix for processing in the plurality of circuits in an order where columns processed concurrently by the plurality of circuits in pipeline stages include no more than one parity column of the parity matrix.

公开(公告)号：US12072764B2

公开(公告)日：2024-08-27

申请号：US18048283

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Chandrakanth Rapalli ,  Yoav Weinberg ,  Tal Sharifie

IPC: G06F11/10

CPC classification number: G06F11/108 ,  G06F11/106

Abstract: Methods, systems, and devices for command and data path error protection are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

公开(公告)号：US12067264B2

公开(公告)日：2024-08-20

申请号：US17829920

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Yoav Weinberg

IPC: G06F3/06

CPC classification number: G06F3/0623 ,  G06F3/0655 ,  G06F3/0679

Abstract: A processing device in a memory sub-system receives a request to perform a memory access operation on a memory device, determines a memory segment identifier associated with the memory access operation, and applies a hash function to the memory segment identifier to generate a hashed seed. The processing device further provides the hashed seed to a pseudo-random number generator to generate a randomized string, and performs the memory access operation on the memory device using the randomized string.

公开(公告)号：US11996860B2

公开(公告)日：2024-05-28

申请号：US17829924

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Mustafa N. Kaynak ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: H03M13/00 ,  H03M13/11

CPC classification number: H03M13/1108 ,  H03M13/1128 ,  H03M13/1148 ,  H03M13/6511

Abstract: A processing device in a memory sub-system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device further determines a syndrome for the sense word using the plurality of parity check equation results and determines whether the syndrome for the sense word satisfies a codeword criterion. Responsive to the syndrome for the sense word not satisfying the codeword criterion, the processing device performs an iterative low density parity check (LDPC) correction process using a scaled bit flip threshold to correct one or more errors in the sense word.

公开(公告)号：US20240134567A1

公开(公告)日：2024-04-25

申请号：US18048292

申请日：2022-10-19

Applicant: Micron Technology, Inc.

Inventor： Chandrakanth Rapalli ,  Yoav Weinberg ,  Tal Sharifie

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0673

Abstract: Methods, systems, and devices for command timer interrupt are described. In some cases, a memory system having a host-driven logical block interface may maintain a timer to measure processing of commands. For example, upon receiving a command and storing the command in a command queue, a protocol controller of the memory system may issue the command to a command controller of the memory system and initiate the timer. Upon receiving a response for the command from the command controller, the protocol controller may reset or stop the timer, depending on whether the command queue is empty. If the timer expires prior to receiving a response for the command, the protocol controller may issue an interrupt signal to the command controller.

公开(公告)号：US20230393765A1

公开(公告)日：2023-12-07

申请号：US17829920

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Yoav Weinberg

IPC: G06F3/06

CPC classification number: G06F3/0623 ,  G06F3/0655 ,  G06F3/0679

Abstract: A processing device in a memory sub-system receives a request to perform a memory access operation on a memory device, determines a memory segment identifier associated with the memory access operation, and applies a hash function to the memory segment identifier to generate a hashed seed. The processing device further provides the hashed seed to a pseudo-random number generator to generate a randomized string, and performs the memory access operation on the memory device using the randomized string.

公开(公告)号：US20230299754A1

公开(公告)日：2023-09-21

申请号：US17696352

申请日：2022-03-16

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz ,  Yoav Weinberg

IPC: H03K3/037

CPC classification number: H03K3/037

Abstract: A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.

公开(公告)号：US20220328109A1

公开(公告)日：2022-10-13

申请号：US17229476

申请日：2021-04-13

Applicant: Micron Technology, Inc.

Inventor： Yoav Weinberg ,  Eric N. Lee

IPC: G11C16/34 ,  G11C16/20 ,  G11C16/26 ,  G11C16/32 ,  G11C7/10

Abstract: A method includes determining, via status polling at a first interval, an indicator of an almost ready status of a set of memory cells of a memory device, based on the indicator of the almost ready status, determining the set of memory cells of the memory device is almost ready to complete execution of an operation on the set of memory cells of the memory device, and responsive to determining the set of memory cells of the memory device is almost ready to complete execution of the operation, performing status polling at a second interval.