公开(公告)号：US11832454B2

公开(公告)日：2023-11-28

申请号：US17396049

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Yi Fang Lee ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Karthik Sarpatwari ,  Scott E. Sills ,  Sameer Chhajed

IPC: H10B99/00 ,  H01L27/092 ,  H01L27/12 ,  H01L29/66 ,  H01L29/267 ,  H01L29/423 ,  H01L29/786 ,  H01L29/24

CPC classification number: H10B99/00 ,  H01L27/092 ,  H01L27/124 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78642

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11538919B2

公开(公告)日：2022-12-27

申请号：US17182808

申请日：2021-02-23

Applicant: Micron Technology, Inc.

Inventor： Ramanathan Gandhi ,  Augusto Benvenuti ,  Giovanni Maria Paolucci

IPC: H01L29/51

Abstract: A transistor comprises a channel region having a frontside and a backside. A gate is adjacent the frontside of the channel region with a gate insulator being between the gate and the channel region. Insulating material having net negative charge is adjacent the backside of the channel region. The insulating material comprises at least one of AlxFy, HfAlxFy, AlOxNy, and HfAlxOyNz, where “x”, “y”, and “z” are each greater than zero. Other embodiments and aspects are disclosed.

公开(公告)号：US11515417B2

公开(公告)日：2022-11-29

申请号：US16596448

申请日：2019-10-08

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Ramanathan Gandhi ,  Durai Vishak Nirmal Ramaswamy ,  Yi Fang Lee ,  Kamal M. Karda

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L27/24

Abstract: A transistor comprises a first conductive contact, a heterogeneous channel comprising at least one oxide semiconductor material over the first conductive contact, a second conductive contact over the heterogeneous channel, and a gate electrode laterally neighboring the heterogeneous channel. A device, a method of forming a device, a memory device, and an electronic system are also described.

公开(公告)号：US20200220022A1

公开(公告)日：2020-07-09

申请号：US16826011

申请日：2020-03-20

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Kirk D. Prall ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi

IPC: H01L29/78 ,  H01L27/11597 ,  H01L29/51 ,  H01L27/11514 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06

Abstract: A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed.

公开(公告)号：US11856766B2

公开(公告)日：2023-12-26

申请号：US17391377

申请日：2021-08-02

Applicant: Micron Technology, Inc.

Inventor： Venkatakrishnan Sriraman ,  Dae Hong Eom ,  Ramanathan Gandhi ,  Donghua Li ,  Ashok Kumar Muthukumaran

IPC: H10B43/27 ,  H10B41/27 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66

CPC classification number: H10B41/27 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792 ,  H10B43/27

Abstract: A memory cell comprises channel material, charge-passage material, programmable material, a charge-blocking region, and a control gate. The programmable material comprises at least two regions comprising SiNx having a region comprising SiOy therebetween, where “x” is 0.5 to 3.0 and “y” is 1.0 to 3.0. Methods are disclosed.

公开(公告)号：US11695050B2

公开(公告)日：2023-07-04

申请号：US17194971

申请日：2021-03-08

Applicant: Micron Technology, Inc.

Inventor： Ramanathan Gandhi

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L29/4234 ,  H01L29/4958 ,  H10B43/10 ,  H10B43/27

Abstract: Some embodiments include a memory cell having a conductive gate comprising ruthenium. A charge-blocking region is adjacent the conductive gate, a charge-storage region is adjacent the charge-blocking region, a tunneling material is adjacent the charge-storage region, and a channel material is adjacent the tunneling material. Some embodiments include an assembly having a vertical stack of alternating insulative levels and wordline levels. The wordline levels contain conductive wordline material which includes ruthenium. Semiconductor material extends through the stack as a channel structure. Charge-storage regions are between the conductive wordline material and the channel structure. Charge-blocking regions are between the charge-storage regions and the conductive wordline material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230081634A1

公开(公告)日：2023-03-16

申请号：US18050424

申请日：2022-10-27

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Ramanathan Gandhi ,  Durai Vishak Nirmal Ramaswamy ,  Yi Fang Lee ,  Kamal M. Karda

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L27/24

Abstract: A transistor comprises a first conductive contact, a heterogeneous channel comprising at least one oxide semiconductor material over the first conductive contact, a second conductive contact over the heterogeneous channel, and a gate electrode laterally neighboring the heterogeneous channel. A device, a method of forming a device, a memory device, and an electronic system are also described.

公开(公告)号：US11437521B2

公开(公告)日：2022-09-06

申请号：US16596487

申请日：2019-10-08

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Ramanathan Gandhi ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L29/66 ,  H01L29/786 ,  H01L27/24

Abstract: A method of forming a device comprises forming dielectric structures over other dielectric structures overlying conductive contact structures, the dielectric structures separated from one another by trenches and laterally extending orthogonal to the other dielectric structures and the conductive contact structures. Conductive gate structures are formed on exposed side surfaces of the dielectric structures within the trenches. Dielectric oxide structures are formed on exposed side surfaces of the conductive gate structures within the trenches. Exposed portions of the other dielectric structures are removed to form isolation structures. Semiconductive pillars are formed on exposed side surfaces of the dielectric oxide structures and the isolation structures within the trenches. The semiconductive pillars are in electrical contact with the conductive contact structures. Additional conductive contact structures are formed on upper surfaces of the semiconductive pillars. A device, a memory device, and an electronic system are also described.

公开(公告)号：US20220271142A1

公开(公告)日：2022-08-25

申请号：US17182808

申请日：2021-02-23

Applicant: Micron Technology, Inc.

Inventor： Ramanathan Gandhi ,  Augusto Benvenuti ,  Giovanni Maria Paolucci

IPC: H01L29/51

Abstract: A transistor comprises a channel region having a frontside and a backside. A gate is adjacent the frontside of the channel region with a gate insulator being between the gate and the channel region. Insulating material having net negative charge is adjacent the backside of the channel region. The insulating material comprises at least one of AlxFy, HfAlxFy, AlOxNy, and HfAlxOyNz, where “x”, “y”, and “z” are each greater than zero. Other embodiments and aspects are disclosed.

公开(公告)号：US20200328280A1

公开(公告)日：2020-10-15

申请号：US16383964

申请日：2019-04-15

Applicant: Micron Technology, Inc.

Inventor： Ramanathan Gandhi

IPC: H01L29/423 ,  H01L27/11582 ,  H01L27/11565 ,  H01L29/49

Abstract: Some embodiments include a memory cell having a conductive gate comprising ruthenium. A charge-blocking region is adjacent the conductive gate, a charge-storage region is adjacent the charge-blocking region, a tunneling material is adjacent the charge-storage region, and a channel material is adjacent the tunneling material. Some embodiments include an assembly having a vertical stack of alternating insulative levels and wordline levels. The wordline levels contain conductive wordline material which includes ruthenium. Semiconductor material extends through the stack as a channel structure. Charge-storage regions are between the conductive wordline material and the channel structure. Charge-blocking regions are between the charge-storage regions and the conductive wordline material. Some embodiments include methods of forming integrated assemblies.