公开(公告)号：US20120025309A1

公开(公告)日：2012-02-02

申请号：US12846457

申请日：2010-07-29

申请人： Chun-Hung Chen ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

发明人： Chun-Hung Chen ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/513 ,  H01L29/495

摘要： An offset gate semiconductor device includes a substrate and an isolation feature formed in the substrate. An active region is formed in the substrate substantially adjacent to the isolation feature. An interface layer is formed on the substrate over the isolation feature and the active region. A polysilicon layer is formed on the interface layer over the isolation feature and the active region. A trench being formed in the polysilicon layer over the isolation feature. The trench extending to the interface layer. A fill layer is formed to line the trench and a metal gate formed in the trench.

摘要翻译： 偏移门半导体器件包括衬底和形成在衬底中的隔离特征。 在基板上基本上与隔离特征相邻地形成有源区。 在隔离特征和有源区上的衬底上形成界面层。 在隔离特征和有源区上的界面层上形成多晶硅层。 在隔离特征上形成在多晶硅层中的沟槽。 沟槽延伸到界面层。 形成填充层以在沟槽中形成沟槽和形成的金属栅极。

公开(公告)号：US09070784B2

公开(公告)日：2015-06-30

申请号：US13189232

申请日：2011-07-22

申请人： Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

发明人： Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

IPC分类号： H01L21/338 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/3212 ,  H01L21/82385 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0642

摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate, an N-metal gate electrode, and a P-metal gate electrode. The substrate comprises an isolation region surrounding a P-active region and an N-active region. The N-metal gate electrode comprises a first metal composition over the N-active region. The P-metal gate electrode comprises a bulk portion over the P-active region and an endcap portion over the isolation region. The endcap portion comprises the first metal composition and the bulk portion comprises a second metal composition different from the first metal composition.

摘要翻译： 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括衬底，N金属栅电极和P金属栅电极。 衬底包括围绕P活性区域和N-活性区域的隔离区域。 所述N-金属栅电极包括在所述N-活性区上的第一金属组合物。 P型金属栅电极包括位于P有源区上的本体部分和在隔离区上方的端盖部分。 端盖部分包括第一金属组合物，并且本体部分包含不同于第一金属组合物的第二金属组合物。

公开(公告)号：US08183644B1

公开(公告)日：2012-05-22

申请号：US13025956

申请日：2011-02-11

申请人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Ming Zhu ,  Hui-Wen Lin ,  Lee-Wee Teo

发明人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Ming Zhu ,  Hui-Wen Lin ,  Lee-Wee Teo

IPC分类号： H01L21/027

CPC分类号： H01L21/823842 ,  H01L21/823871

摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising a P-active region, an N-active region, and an isolation region interposed between the P- and N-active regions; a P-metal gate electrode over the P-active region, that extends over the isolation region; and an N-metal gate electrode having a first width over the N-active region, that extends over the isolation region and has a contact section in the isolation region electrically contacting the P-metal gate electrode, wherein the contact section has a second width greater than the first width.

摘要翻译： 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括：衬底，其包括P活性区域，N活性区域和插入在P-活性区域和N - 活性区域之间的隔离区域; 在P-活性区域上的P金属栅极电极，其在隔离区域上延伸; 以及在所述N-有源区上具有第一宽度的N-金属栅电极，其在所述隔离区上延伸，并且在所述隔离区中具有与所述P金属栅电极电接触的接触部，其中所述接触部具有第二宽度 大于第一宽度。

公开(公告)号：US20120001259A1

公开(公告)日：2012-01-05

申请号：US12830107

申请日：2010-07-02

申请人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Jin-Aun Ng ,  Wei Cheng Wu ,  Ming Zhu

发明人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Jin-Aun Ng ,  Wei Cheng Wu ,  Ming Zhu

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L21/823481 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/66545

摘要： A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.

摘要翻译： 一种方法包括提供具有第一表面的基板，形成部分地设置在基板中的隔离结构，并且具有高于第一表面的台阶高度的第二表面，去除隔离结构的一部分以形成其中具有底部 表面与所述第一表面间隔开小于所述台阶高度，形成栅极结构，以及形成在所述凹部上接合所述栅极结构的触点。 不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有 与所述第一表面间隔小于所述台阶高度的底表面，栅极结构以及在所述凹部上接合所述栅极结构的触点。

公开(公告)号：US08329521B2

公开(公告)日：2012-12-11

申请号：US12830107

申请日：2010-07-02

申请人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Jin-Aun Ng ,  Wei Cheng Wu ,  Ming Zhu

发明人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Jin-Aun Ng ,  Wei Cheng Wu ,  Ming Zhu

IPC分类号： H01L21/8238 ,  H01L27/148

CPC分类号： H01L21/823481 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/66545

摘要： A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.

摘要翻译： 一种方法包括提供具有第一表面的基板，形成部分地设置在基板中的隔离结构，并且具有高于第一表面的台阶高度的第二表面，去除隔离结构的一部分以形成其中具有底部 表面与所述第一表面间隔开小于所述台阶高度，形成栅极结构，以及形成在所述凹部上接合所述栅极结构的触点。 不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有 与所述第一表面间隔小于所述台阶高度的底表面，栅极结构以及在所述凹部上接合所述栅极结构的触点。

公开(公告)号：US08258584B2

公开(公告)日：2012-09-04

申请号：US12846457

申请日：2010-07-29

申请人： Chun-Hung Chen ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

发明人： Chun-Hung Chen ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/513 ,  H01L29/495

摘要： An offset gate semiconductor device includes a substrate and an isolation feature formed in the substrate. An active region is formed in the substrate substantially adjacent to the isolation feature. An interface layer is formed on the substrate over the isolation feature and the active region. A polysilicon layer is formed on the interface layer over the isolation feature and the active region. A trench being formed in the polysilicon layer over the isolation feature. The trench extending to the interface layer. A fill layer is formed to line the trench and a metal gate formed in the trench.

摘要翻译： 偏移门半导体器件包括衬底和形成在衬底中的隔离特征。 在基板上基本上与隔离特征相邻地形成有源区。 在隔离特征和有源区上的衬底上形成界面层。 在隔离特征和有源区上的界面层上形成多晶硅层。 在隔离特征上形成在多晶硅层中的沟槽。 沟槽延伸到界面层。 形成填充层以在沟槽中形成沟槽和形成的金属栅极。

公开(公告)号：US08890260B2

公开(公告)日：2014-11-18

申请号：US12554604

申请日：2009-09-04

申请人： Harry Hak-Lay Chuang ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Chiung-Han Yeh ,  Lee-Wee Teo ,  Yu-Ying Hsu ,  Bao-Ru Young

发明人： Harry Hak-Lay Chuang ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Chiung-Han Yeh ,  Lee-Wee Teo ,  Yu-Ying Hsu ,  Bao-Ru Young

IPC分类号： H01L29/78 ,  H01L27/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L49/02

CPC分类号： H01L29/66545 ,  H01L21/823842 ,  H01L27/0629 ,  H01L27/0802 ,  H01L27/0922 ,  H01L28/20 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2223/6672

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

摘要翻译： 本发明提供集成电路。 集成电路包括半导体衬底; 以及设置在半导体衬底上的无源多晶硅器件。 无源多晶硅器件还包括多晶硅特征; 以及嵌入在多晶硅特征中的多个电极。

公开(公告)号：US08524570B2

公开(公告)日：2013-09-03

申请号：US12890995

申请日：2010-09-27

申请人： Harry Hak-Lay Chuang ,  Chih-Yang Yeh ,  Bao-Ru Young ,  Yuh-Jier Mii

发明人： Harry Hak-Lay Chuang ,  Chih-Yang Yeh ,  Bao-Ru Young ,  Yuh-Jier Mii

IPC分类号： H01L21/76

CPC分类号： H01L29/78 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088

摘要： A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess.

摘要翻译： 一种制造半导体器件的方法包括提供具有第一表面的衬底，形成部分地设置在衬底中的隔离结构，并且具有高于第一表面的第二表面，台阶高度，去除隔离结构的一部分以形成 在其中具有设置在第一表面下方的底表面的凹槽，以及形成在凹部上方接合栅极结构的触点。 不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有 设置在第一表面下方的底表面，栅极结构，以及在凹部上接合栅极结构的触点。

公开(公告)号：US20130285151A1

公开(公告)日：2013-10-31

申请号：US13457079

申请日：2012-04-26

申请人： Wei Cheng Wu ,  Po-Nien Chen ,  Jin-Aun Ng ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

发明人： Wei Cheng Wu ,  Po-Nien Chen ,  Jin-Aun Ng ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

IPC分类号： H01L27/092 ,  H01L21/336

CPC分类号： H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0629 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

公开(公告)号：US20120074498A1

公开(公告)日：2012-03-29

申请号：US12890995

申请日：2010-09-27

申请人： Harry Hak-Lay Chuang ,  Chih-Yang Yeh ,  Bao-Ru Young ,  Yuh-Jier Mii

发明人： Harry Hak-Lay Chuang ,  Chih-Yang Yeh ,  Bao-Ru Young ,  Yuh-Jier Mii

IPC分类号： H01L21/762 ,  H01L27/088

CPC分类号： H01L29/78 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088

摘要： A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess.

摘要翻译： 一种制造半导体器件的方法包括提供具有第一表面的衬底，形成部分地设置在衬底中的隔离结构，并且具有高于第一表面的第二表面，台阶高度，去除隔离结构的一部分以形成 在其中具有设置在第一表面下方的底表面的凹槽，以及形成在凹部上方接合栅极结构的触点。 不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有 设置在第一表面下方的底表面，栅极结构，以及在凹部上接合栅极结构的触点。