公开(公告)号：US06329718B1

公开(公告)日：2001-12-11

申请号：US09105775

申请日：1998-06-26

申请人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick MacCrae ,  Richard J. Huang ,  Khanh Tran

发明人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick MacCrae ,  Richard J. Huang ,  Khanh Tran

IPC分类号： H01L2348

CPC分类号： H01L21/7685 ,  H01L21/76837 ,  H01L21/76858 ,  H01L21/76885 ,  H01L23/53223 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

摘要翻译： 用于制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。 在退火期间，形成铝和钛的合金，其随后容积收缩，收缩被铝吸收。 因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。 因此，互连线中不希望的空隙形成的可能性降低。 在随后的ILD间隙填充沉积过程中，通过使用相对低的偏置功率来降低气相沉积温度，并且通过使用相对较低的源气体沉积流速来减少互连线上的流动引起的压缩应力，仍然进一步降低了不希望的空隙形成的可能性 在ILD形成期间。

公开(公告)号：US06492258B1

公开(公告)日：2002-12-10

申请号：US09881831

申请日：2001-06-14

申请人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick Maccrae ,  Richard J. Huang ,  Khanh Tran

发明人： Minh Van Ngo ,  Paul R. Besser ,  Matthew Buynoski ,  John Caffall ,  Nick Maccrae ,  Richard J. Huang ,  Khanh Tran

IPC分类号： H01L214763

CPC分类号： H01L21/7685 ,  H01L21/76837 ,  H01L21/76858 ,  H01L21/76885 ,  H01L23/53223 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation. in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature. and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

摘要翻译： 制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。 在退火期间，形成铝和钛的合金，其随后容积收缩，铝的收缩被铝吸收。 因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。 因此，形成不希望的空隙的可能性。 在互连线路中减少。 在随后的ILD间隙填充沉积过程中，通过使用相对低的偏压功率来降低气相沉积温度，仍然进一步降低了不希望的空隙形成的可能性。 并且通过使用相对低的源气体沉积流速来减少在ILD形成期间在互连线上的流动引起的压缩应力。

公开(公告)号：US07217660B1

公开(公告)日：2007-05-15

申请号：US11109964

申请日：2005-04-19

申请人： Connie Pin-Chin Wang ,  Paul R. Besser ,  Jinsong Yin ,  Hieu T. Pham ,  Minh Van Ngo

发明人： Connie Pin-Chin Wang ,  Paul R. Besser ,  Jinsong Yin ,  Hieu T. Pham ,  Minh Van Ngo

IPC分类号： H01L21/22

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76846 ,  H01L29/6659

摘要： A method for manufacturing a semiconductor component that inhibits formation of wormholes in a semiconductor substrate. A contact opening is formed in a dielectric layer disposed on a semiconductor substrate. The contact opening exposes a portion of the semiconductor substrate. A sacrificial layer of oxide is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact opening. Silane is reacted with tungsten hexafluoride to form a hydrofluoric acid vapor and tungsten. The hydrofluoric acid vapor etches away the sacrificial oxide layer and a thin layer of tungsten is formed on the exposed portion of the semiconductor substrate. After forming the thin layer of tungsten, the reactants may be changed to more quickly fill the contact opening with tungsten.

摘要翻译： 一种制造半导体元件的方法，该半导体元件抑制在半导体衬底中形成虫洞。 在设置在半导体衬底上的电介质层中形成接触开口。 接触开口露出半导体衬底的一部分。 在半导体衬底的暴露部分上并沿着接触开口的侧壁形成氧化物牺牲层。 硅烷与六氟化钨反应形成氢氟酸蒸汽和钨。 氢氟酸蒸气蚀刻掉牺牲氧化物层，并且在半导体衬底的暴露部分上形成薄的钨层。 在形成钨的薄层之后，可以改变反应物以更快地用钨填充接触开口。

公开(公告)号：US07049666B1

公开(公告)日：2006-05-23

申请号：US10859286

申请日：2004-06-01

申请人： Robert J. Chiu ,  Jeffrey P. Patton ,  Paul R. Besser ,  Minh Van Ngo

发明人： Robert J. Chiu ,  Jeffrey P. Patton ,  Paul R. Besser ,  Minh Van Ngo

IPC分类号： H01L29/94 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin insulating layer is formed over the source/drain junctions. A silicide is formed on the thin insulating layer and on the gate. An interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结上形成一个薄的绝缘层。 在薄绝缘层和栅极上形成硅化物。 在半导体衬底上沉积层间电介质。 然后在层间电介质中形成与硅化物的接触。

公开(公告)号：US06661067B1

公开(公告)日：2003-12-09

申请号：US10260514

申请日：2002-10-01

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser ,  Robert A. Huertas

IPC分类号： H01L2994

CPC分类号： H01L29/665 ,  H01L21/3115 ,  Y10S257/90

摘要： Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

摘要翻译： 通过用氮等离子体处理氮化硅侧壁间隔物的暴露表面来形成具有减少的游离硅的表面区域，防止栅电极上的硅化镍层与沿着氮化硅侧壁间隔物的源/漏区之间的桥接。 实施例包括用氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

公开(公告)号：US06602754B1

公开(公告)日：2003-08-05

申请号：US10059039

申请日：2002-01-30

申请人： George J. Kluth ,  Minh Van Ngo ,  Paul R. Besser

发明人： George J. Kluth ,  Minh Van Ngo ,  Paul R. Besser

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/265

摘要： Bridging between silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by implanting the exposed surfaces of the silicon nitride sidewall spacers with nitrogen to create a surface region having an increased nitrogen concentration. Embodiments include implanting the silicon nitride sidewall spacers with nitrogen such that the nitrogen concentration of the exposed surface is increased by about 5% to about 15%, thereby substantially preventing the formation of metal silicide on the sidewall spacers.

摘要翻译： 通过用氮气注入氮化硅侧壁间隔物的暴露表面以产生具有增加的氮浓度的表面区域来防止在栅电极上的硅化物层与沿着氮化硅侧壁间隔物的源/漏区之间的桥接。 实施例包括用氮气注入氮化硅侧壁间隔物，使得暴露表面的氮浓度增加约5％至约15％，从而基本上防止在侧壁间隔物上形成金属硅化物。

公开(公告)号：US06432805B1

公开(公告)日：2002-08-13

申请号：US09783620

申请日：2001-02-15

申请人： Eric N. Paton ,  Minh Van Ngo ,  Paul R. Besser

发明人： Eric N. Paton ,  Minh Van Ngo ,  Paul R. Besser

IPC分类号： H01L213205

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518

摘要： Salicide processing is implemented with silicon nitride sidewall spacers by initially depositing a refractory metal, e.g., Ni, in the presence of nitrogen to form a metal nitride layer to prevent the reaction of the deposited metal with free Si in silicon nitride sidewall spacers, thereby avoiding bridging between the metal silicide layer on the gate electrode and the metal silicide layers on the source/drain regions of a semiconductor device.

摘要翻译： 通过在氮气存在下首先沉积难熔金属（例如Ni）以形成金属氮化物层，以防止沉积的金属与氮化硅侧壁间隔物中的游离Si的反应，从而避免了氮化硅侧壁间隔物的剥离处理 桥接在栅电极上的金属硅化物层和半导体器件的源极/漏极区域上的金属硅化物层之间。

公开(公告)号：US06171919B2

公开(公告)日：2001-01-09

申请号：US09361155

申请日：1999-07-27

申请人： Paul R. Besser ,  Minh Van Ngo ,  Simon S. Chan ,  Angela T. Hui

发明人： Paul R. Besser ,  Minh Van Ngo ,  Simon S. Chan ,  Angela T. Hui

IPC分类号： H01L21336

CPC分类号： H01L29/665

摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.

摘要翻译： 通过自对准硅化物工艺形成具有减小的或最小的结泄漏的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中在自对准硅化物处理之前除去由用于侧壁间隔物形成的反应等离子体蚀刻而导致的硅衬底表面上的碳质残渣 。 实施例包括通过进行氢离子等离子体处理来除去碳质残渣。

公开(公告)号：US07422961B2

公开(公告)日：2008-09-09

申请号：US10389456

申请日：2003-03-14

申请人： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

发明人： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.

摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温工艺可以是CVD工艺。

公开(公告)号：US07312125B1

公开(公告)日：2007-12-25

申请号：US10773026

申请日：2004-02-05

申请人： Qi Xiang ,  Paul R. Besser ,  Minh Van Ngo ,  Eric N. Paton ,  Haihong Wang

发明人： Qi Xiang ,  Paul R. Besser ,  Minh Van Ngo ,  Eric N. Paton ,  Haihong Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L27/1203 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7848 ,  H01L29/78621 ,  H01L29/78684 ,  Y10S438/938

摘要： An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and a buried oxide layer. A hydrogen implant can provide a breaking interface to remove a silicon substrate from the silicon germanium layer.

摘要翻译： 集成电路包括多层。 可以使用绝缘体上半导体（SOI）晶片来容纳晶体管。 可以结合两个基板或晶片以形成多个层。 应变半导体层可以在硅锗层和掩埋氧化物层之间。 氢注入可以提供断开界面以从硅锗层去除硅衬底。