公开(公告)号：US09202758B1

公开(公告)日：2015-12-01

申请号：US11109965

申请日：2005-04-19

申请人： Paul R. Besser ,  Minh Van Ngo ,  Connie Pin-Chin Wang ,  Jinsong Yin ,  Hieu T. Pham

发明人： Paul R. Besser ,  Minh Van Ngo ,  Connie Pin-Chin Wang ,  Jinsong Yin ,  Hieu T. Pham

IPC分类号： H01L21/8234 ,  H01L29/49

CPC分类号： H01L21/823418 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component and a method for manufacturing the semiconductor component that are suitable for use with low temperature processing. A semiconductor substrate is provided and an optional layer of silicon nitride is formed on the semiconductor substrate using Atomic Layer Deposition (ALD). A layer of dielectric material is formed on the silicon nitride layer using Sub-Atmospheric Chemical Vapor Deposition (SACVD) at a temperature below about 450° C. When the optional layer of silicon nitride is not present, the SACVD dielectric material is formed on the semiconductor substrate. A contact hole having sidewalls is formed through the SACVD dielectric layer, through the silicon nitride layer, and exposes a portion of the semiconductor substrate. A layer of tungsten nitride is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact hole. Tungsten is formed on the layer of tungsten nitride.

摘要翻译： 适用于低温处理的半导体元件和半导体元件的制造方法。 提供半导体衬底，并且使用原子层沉积（ALD）在半导体衬底上形成任选的氮化硅层。 使用亚大气化学气相沉积（SACVD）在低于约450℃的温度下在氮化硅层上形成介电材料层。当不存在任选的氮化硅层时，SACVD介电材料形成在 半导体衬底。 通过SACVD介电层，通过氮化硅层形成具有侧壁的接触孔，并露出半导体衬底的一部分。 在半导体衬底的暴露部分和接触孔的侧壁上形成氮化钨层。 在氮化钨层上形成钨。

公开(公告)号：US07217660B1

公开(公告)日：2007-05-15

申请号：US11109964

申请日：2005-04-19

申请人： Connie Pin-Chin Wang ,  Paul R. Besser ,  Jinsong Yin ,  Hieu T. Pham ,  Minh Van Ngo

发明人： Connie Pin-Chin Wang ,  Paul R. Besser ,  Jinsong Yin ,  Hieu T. Pham ,  Minh Van Ngo

IPC分类号： H01L21/22

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76846 ,  H01L29/6659

摘要： A method for manufacturing a semiconductor component that inhibits formation of wormholes in a semiconductor substrate. A contact opening is formed in a dielectric layer disposed on a semiconductor substrate. The contact opening exposes a portion of the semiconductor substrate. A sacrificial layer of oxide is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact opening. Silane is reacted with tungsten hexafluoride to form a hydrofluoric acid vapor and tungsten. The hydrofluoric acid vapor etches away the sacrificial oxide layer and a thin layer of tungsten is formed on the exposed portion of the semiconductor substrate. After forming the thin layer of tungsten, the reactants may be changed to more quickly fill the contact opening with tungsten.

摘要翻译： 一种制造半导体元件的方法，该半导体元件抑制在半导体衬底中形成虫洞。 在设置在半导体衬底上的电介质层中形成接触开口。 接触开口露出半导体衬底的一部分。 在半导体衬底的暴露部分上并沿着接触开口的侧壁形成氧化物牺牲层。 硅烷与六氟化钨反应形成氢氟酸蒸汽和钨。 氢氟酸蒸气蚀刻掉牺牲氧化物层，并且在半导体衬底的暴露部分上形成薄的钨层。 在形成钨的薄层之后，可以改变反应物以更快地用钨填充接触开口。

公开(公告)号：US07476604B1

公开(公告)日：2009-01-13

申请号：US11128391

申请日：2005-05-13

申请人： Ning Cheng ,  Minh Van Ngo ,  Jinsong Yin ,  Paul Raymond Besser ,  Connie Pin-chin Wang ,  Russell Rosaire Austin Callahan ,  Jeffrey Shields ,  Shankar Sinha ,  Jeff P. Erhardt ,  Jeremy Chi-Hung Chou

发明人： Ning Cheng ,  Minh Van Ngo ,  Jinsong Yin ,  Paul Raymond Besser ,  Connie Pin-chin Wang ,  Russell Rosaire Austin Callahan ,  Jeffrey Shields ,  Shankar Sinha ,  Jeff P. Erhardt ,  Jeremy Chi-Hung Chou

IPC分类号： H01L21/44

CPC分类号： H01L21/76831 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855

摘要： A method of forming a contact through a material includes forming a via through a dielectric material and cleaning the via using a dilute hydrofluoric (DHF) acid solution. The method further includes depositing a barrier layer within the via and depositing metal adjacent the barrier layer.

摘要翻译： 通过材料形成接触的方法包括通过电介质材料形成通孔，并使用稀氢氟酸（DHF）酸溶液清洗通孔。 所述方法还包括在所述通孔内沉积阻挡层并在所述阻挡层附近沉积金属。

公开(公告)号：US06861350B1

公开(公告)日：2005-03-01

申请号：US10464508

申请日：2003-06-19

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Jinsong Yin ,  James Pan ,  Paul R. Besser

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Jinsong Yin ,  James Pan ,  Paul R. Besser

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H10L21/4763 ,  H10L21/44

CPC分类号： H01L29/66606 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545

摘要： Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 Å to 75 Å, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.

摘要翻译： 微型半导体器件由富含硅的钽氮化硅替代金属栅电极制成。 实施例包括去除可移除栅极，通过PVD沉积氮化钽层，厚度为25埃，然后通过在硅烷或硅烷等离子体处理中热浸泡形成层，将硅引入沉积的氮化钽层中 的富硅钽硅氮化物。 在另一个实施方案中，在沉积氮化钽层之前和之后，使中间体在硅烷或硅烷等离子体处理中进行热浸。 实施例还包括在沉积氮化钽层之前用硅烷预处理中间结构，用硅烷处理沉积的氮化钽层，并重复这些步骤多次以形成多个富硅钽硅氮化物的子层。

公开(公告)号：US07033888B2

公开(公告)日：2006-04-25

申请号：US10806117

申请日：2004-03-23

申请人： James N. Pan ,  Paul R. Besser ,  Christy Woo ,  Minh Van Ngo ,  Jinsong Yin

发明人： James N. Pan ,  Paul R. Besser ,  Christy Woo ,  Minh Van Ngo ,  Jinsong Yin

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L29/4966

摘要： A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.

摘要翻译： 形成具有固有电场的金属栅电极，以改变晶体管的功函数和阈值电压。 实施例包括通过去除可移除栅极来形成电介质层中的开口，沉积一层或多层氮化钽，使氮含量从邻近栅介质层的层的底部向上增加。 其他实施例包括通过掺杂一个或多个金属层并形成金属合金来形成本征电场以控制功函数。 实施例还包括在形成金属栅电极时使用阻挡层。

公开(公告)号：US07060571B1

公开(公告)日：2006-06-13

申请号：US10777138

申请日：2004-02-13

申请人： Minh Van Ngo ,  Christy Woo ,  James Pan ,  Paul R. Besser ,  Jinsong Yin

发明人： Minh Van Ngo ,  Christy Woo ,  James Pan ,  Paul R. Besser ,  Jinsong Yin

IPC分类号： H01L21/336

CPC分类号： H01L21/28229 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： Microminiaturized semiconductor devices are fabricated with a replacement metal gate and a high-k tantalum oxide or tantalum oxynitride gate dielectric with significantly reduced carbon. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing a thin tantalum film, as by PVD at a thickness of 25 Å to 60 Å lining the opening, and then conducting thermal oxidation, as at a temperature of 100° C. to 500° C., in flowing oxygen or ozone to form a high-k tantalum oxide gate dielectric layer, or in oxygen and N2O or ozone and N2O ammonia to form a high-k tantalum oxynitride gate dielectric. Alternatively, oxidation can be conducted in an oxygen or ozone plasma to form the high-k tantalum oxide layer, or in a plasma containing N2O and oxygen or ozone to form the high-k tantalum oxynitride gate dielectric layer.

摘要翻译： 微型半导体器件由具有显着降低的碳的替代金属栅极和高k钽氧化物或氮氧化钽栅极电介质制成。 实施例包括通过去除可移除栅极来形成电介质层中的开口，沉积薄的钽膜，如通过PVD覆盖厚度为25埃至60埃的开口，然后在100℃的温度下进行热氧化 在500℃下，在流动的氧气或臭氧中形成高k氧化钽栅极电介质层，或在氧和N 2 O或臭氧和N 2 O 3 > O氨形成高k钽氮氧化物栅极电介质。 或者，可以在氧气或臭氧等离子体中进行氧化以形成高k钽氧化物层，或者在含有N 2 O的氧化物或臭氧的等离子体中进行氧化以形成高k氮氧化钽栅极 电介质层。

公开(公告)号：US06893910B1

公开(公告)日：2005-05-17

申请号：US10462670

申请日：2003-06-17

申请人： Christy Mei-Chu Woo ,  Paul R. Besser ,  Minh Van Ngo ,  James N. Pan ,  Jinsong Yin

发明人： Christy Mei-Chu Woo ,  Paul R. Besser ,  Minh Van Ngo ,  James N. Pan ,  Jinsong Yin

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/338 ,  H01L21/31 ,  H01L21/3205

CPC分类号： H01L21/28185 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/31683 ,  H01L29/4958 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833

摘要： A method for forming a semiconductor structure removes the temporary gate formed on the dielectric layer to expose a recess in which oxygen-rich CVD oxide is deposited. A tantalum layer is then deposited by low-power physical vapor deposition on the CVD oxide. Annealing is then performed to create a Ta2O5 region and a Ta region from the deposited oxide and Ta. This creates a low carbon-content Ta2O5 and a metallic Ta gate in a single process step.

摘要翻译： 用于形成半导体结构的方法去除形成在电介质层上的临时栅极以暴露其中沉积有富氧CVD氧化物的凹槽。 然后通过低功率物理气相沉积在CVD氧化物上沉积钽层。 然后进行退火以从沉积的氧化物和Ta形成Ta 2 O 5区域和Ta区域。 这在单一工艺步骤中产生低碳含量的Ta 2 O 5 O 5和金属Ta浇口。

公开(公告)号：US06727560B1

公开(公告)日：2004-04-27

申请号：US10360719

申请日：2003-02-10

申请人： James N. Pan ,  Paul R. Besser ,  Christy Woo ,  Minh Van Ngo ,  Jinsong Yin

发明人： James N. Pan ,  Paul R. Besser ,  Christy Woo ,  Minh Van Ngo ,  Jinsong Yin

IPC分类号： H01L2976

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L29/4966

摘要： A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.

公开(公告)号：US20090050471A1

公开(公告)日：2009-02-26

申请号：US11844518

申请日：2007-08-24

申请人： Robert J. Chiu ,  Connie Pin-Chin Wang ,  Minh Van Ngo ,  Simon S. Chan

发明人： Robert J. Chiu ,  Connie Pin-Chin Wang ,  Minh Van Ngo ,  Simon S. Chan

IPC分类号： C23C14/32

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76814 ,  H01L23/485

摘要： A process of forming an electronic device can include depositing a first layer over a substrate and depositing a second layer over the first layer. In one embodiment, depositing the first layer is performed at a first alternating current (“AC”) power, and depositing the second layer is performed at a second AC power that is different from the first AC power. In another embodiment, the first layer is formed by a physical vapor deposition technique at a first power sufficient to remove the insulating layer using first metal ions, wherein the first layer includes an overhanging portion extending over the bottom of the opening. In a further embodiment, the second layer is formed by the physical vapor deposition technique using second metal ions and a second power sufficient to reduce a lateral dimension of the overhanging portion.

摘要翻译： 形成电子器件的过程可以包括在衬底上沉积第一层并在第一层上沉积第二层。 在一个实施例中，在第一交流（“AC”）功率下执行沉积第一层，并且以不同于第一AC电力的第二AC电源执行沉积第二层。 在另一个实施例中，第一层通过物理气相沉积技术以足以使用第一金属离子去除绝缘层的第一功率形成，其中第一层包括在开口底部延伸的伸出部分。 在另一个实施例中，第二层通过使用第二金属离子的物理气相沉积技术和足以减少突出部分的横向尺寸的第二功率形成。

公开(公告)号：US06746971B1

公开(公告)日：2004-06-08

申请号：US10314060

申请日：2002-12-05

申请人： Minh Van Ngo ,  Sergey D. Lopatin ,  Suzette K. Pangrle ,  Nicholas H. Tripsas ,  Hieu T. Pham

发明人： Minh Van Ngo ,  Sergey D. Lopatin ,  Suzette K. Pangrle ,  Nicholas H. Tripsas ,  Hieu T. Pham

IPC分类号： H01L2131

CPC分类号： H01L51/0036 ,  B82Y10/00 ,  G11C13/0009 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/025 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/28 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0038 ,  H01L51/0041 ,  H01L51/005 ,  H01L51/0053 ,  H01L51/0059 ,  H01L51/0077 ,  H01L51/0081 ,  H01L51/0084 ,  H01L51/0085

摘要： An organic memory cell made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The controllably conductive media changes its impedance when an external stimuli such as an applied electric field is imposed thereon. Methods of making the organic memory devices/cells, methods of using the organic memory devices/cells, and devices such as computers containing the organic memory devices/cells are also disclosed.

摘要翻译： 公开了一种由在两个电极之间具有可控导电介质的两个电极制成的有机存储单元。 可控导电介质包含有机半导体层和无源层。 当施加外部刺激（例如施加的电场）时，可控导电介质改变其阻抗。 还公开了制造有机存储器件/单元的方法，使用有机存储器件/单元的方法，以及诸如包含有机存储器件/单元的计算机的器件。