公开(公告)号：US10360031B2

公开(公告)日：2019-07-23

申请号：US14376825

申请日：2011-10-21

Applicant: Mandeep Singh ,  Mohammad Abdallah

Inventor： Mandeep Singh ,  Mohammad Abdallah

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F13/16 ,  G06F12/0888

Abstract: Fast unaligned memory access. In accordance with a first embodiment of the present invention, a computing device includes a load queue memory structure configured to queue load operations and a store queue memory structure configured to queue store operations. The computing device includes also includes at least one bit configured to indicate the presence of an unaligned address component for an entry of said load queue memory structure, and at least one bit configured to indicate the presence of an unaligned address component for an entry of said store queue memory structure. The load queue memory may also include memory configured to indicate data forwarding of an unaligned address component from said store queue memory structure to said load queue memory structure.

公开(公告)号：US09766893B2

公开(公告)日：2017-09-19

申请号：US13428440

申请日：2012-03-23

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  G06F9/34

CPC classification number: G06F9/3009 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/34 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/5038 ,  G06F9/5077 ,  G06F2209/506 ,  Y02D10/22 ,  Y02D10/36

Abstract: A method for executing instructions using a plurality of virtual cores for a processor. The method includes receiving an incoming instruction sequence using a global front end scheduler, and partitioning the incoming instruction sequence into a plurality of code blocks of instructions. The method further includes generating a plurality of inheritance vectors describing interdependencies between instructions of the code blocks, and allocating the code blocks to a plurality of virtual cores of the processor, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines. The code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors.

公开(公告)号：US20170262287A1

公开(公告)日：2017-09-14

申请号：US13824013

申请日：2011-09-16

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/3806 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30047 ,  G06F9/3804 ,  G06F9/3836 ,  G06F9/3844 ,  G06F9/3869 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/452

Abstract: A method of identifying instructions including accessing a plurality of instructions that comprise multiple branch instructions. For each branch instruction of the multiple branch instructions, a respective first mask is generated representing instructions that are executed if a branch is taken. A respective second mask is generated representing instructions that are executed if the branch is not taken. A prediction output is received that comprises a respective branch prediction for each branch instruction. For each branch instruction, the prediction output is used to select a respective resultant mask from among the respective first and second masks. For each branch instruction, a resultant mask of a subsequent branch is invalidated if a previous branch is predicted to branch over said subsequent branch. A logical operation is performed on all resultant masks to produce a final mask. The final mask is used to select a subset of instructions for execution.

公开(公告)号：US09678755B2

公开(公告)日：2017-06-13

申请号：US13879365

申请日：2011-10-12

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3861 ,  G06F9/30058 ,  G06F9/3808 ,  G06F9/3844

Abstract: A method for outputting alternative instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor. A frequently miss-predicted branch instruction is identified, wherein the predicted outcome of the branch instruction is frequently wrong. An alternative instruction sequence for the branch instruction target is stored into a buffer. On a subsequent hit to the branch instruction where the predicted outcome of the branch instruction was wrong, the alternative instruction sequence is output from the buffer.

公开(公告)号：US09542187B2

公开(公告)日：2017-01-10

申请号：US13359817

申请日：2012-01-27

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/45 ,  G06F9/32 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455

CPC classification number: G06F9/322 ,  G06F9/30058 ,  G06F9/30174 ,  G06F9/3808 ,  G06F9/3844 ,  G06F9/3863 ,  G06F9/4552

Abstract: A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions comprising at least one guest far branch, and building an instruction sequence from the plurality of guest instructions by using branch prediction on the at least one guest far branch. The method further includes assembling a guest instruction block from the instruction sequence. The guest instruction block is translated to a corresponding native conversion block, wherein an at least one native far branch that corresponds to the at least one guest far branch and wherein the at least one native far branch includes an opposite guest address for an opposing branch path of the at least one guest far branch. Upon encountering a missprediction, a correct instruction sequence is obtained by accessing the opposite guest address.

Abstract translation: 一种用于翻译处理器的指令的方法。 该方法包括：访问包括至少一个来宾远分支的多个客运分支指令的多个访客指令，以及通过在至少一个来宾远分支上使用分支预测来从多个访客指令构建指令序列。 所述方法还包括从所述指令序列组装来宾指令块。 访客指令块被转换为相应的本机转换块，其中对应于至少一个来宾远分支的至少一个本地远分支，并且其中所述至少一个本地远分支包括用于相对分支路径的相对的访客地址 的至少一个客户远分支。 在遇到错误预测时，通过访问相对的访客地址获得正确的指令序列。

公开(公告)号：US09442772B2

公开(公告)日：2016-09-13

申请号：US13475739

申请日：2012-05-18

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/50 ,  G06F15/80 ,  G06F9/38 ,  G06F9/30 ,  G06F9/52 ,  G06F9/48 ,  G06F9/46

CPC classification number: G06F9/5077 ,  G06F9/3012 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/46 ,  G06F9/4881 ,  G06F9/52 ,  G06F13/4068 ,  G06F15/80

Abstract: A global interconnect system. The global interconnect system includes a plurality of resources having data for supporting the execution of multiple code sequences and a plurality of engines for implementing the execution of the multiple code sequences. A plurality of resource consumers are within each of the plurality of engines. A global interconnect structure is coupled to the plurality of resource consumers and coupled to the plurality of resources to enable data access and execution of the multiple code sequences, wherein the resource consumers access the resources through a per cycle utilization of the global interconnect structure.

Abstract translation: 全球互连系统。 全局互连系统包括具有用于支持多个代码序列的执行的数据的多个资源和用于实现多个代码序列的执行的多个引擎。 多个资源消耗者在多个发动机的每一个内。 全局互连结构耦合到多个资源使用者，并耦合到多个资源，以实现多个代码序列的数据访问和执行，其中资源使用者通过全局互连结构的每周期利用来访问资源。

公开(公告)号：US09424046B2

公开(公告)日：2016-08-23

申请号：US13649505

申请日：2012-10-11

Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/00 ,  G06F9/38 ,  G06F12/02 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/3842 ,  G06F9/3861 ,  G06F12/0215 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/452

Abstract: Systems and methods for load canceling in a processor that is connected to an external interconnect fabric are disclosed. As a part of a method for load canceling in a processor that is connected to an external bus, and responsive to a flush request and a corresponding cancellation of pending speculative loads from a load queue, a type of one or more of the pending speculative loads that are positioned in the instruction pipeline external to the processor, is converted from load to prefetch. Data corresponding to one or more of the pending speculative loads that are positioned in the instruction pipeline external to the processor is accessed and returned to cache as prefetch data. The prefetch data is retired in a cache location of the processor.

Abstract translation: 公开了在连接到外部互连结构的处理器中用于负载消除的系统和方法。 作为在连接到外部总线的处理器中的负载消除的方法的一部分，并且响应于刷新请求以及来自加载队列的等待的推测负载的相应取消，一种或多种待处理的投机负载 位于处理器外部的指令流水线中，从负载转换为预取。 对应于位于处理器外部的指令流水线中的一个或多个未决投机负载的数据被访问并作为预取数据返回到高速缓存。 预取数据在处理器的高速缓存位置中退出。

公开(公告)号：US20140108739A1

公开(公告)日：2014-04-17

申请号：US13649469

申请日：2012-10-11

Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/00 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383 ,  G06F12/0215 ,  G06F2212/602 ,  G06F2212/6026

Abstract: A method for weak stream software data and instruction prefetching using a hardware data prefetcher is disclosed. A method includes, determining if software includes software prefetch instructions, using a hardware data prefetcher, and, accessing the software prefetch instructions if the software includes software prefetch instructions. Using the hardware data prefetcher, weak stream software data and instruction prefetching operations are executed based on the software prefetch instructions, free of training operations.

Abstract translation: 公开了一种使用硬件数据预取器的弱流软件数据和指令预取方法。 一种方法包括：使用硬件数据预取器来确定软件是否包括软件预取指令，以及如果软件包括软件预取指令，则访问软件预取指令。 使用硬件数据预取器，基于软件预取指令执行弱流软件数据和指令预取操作，无需训练操作。

公开(公告)号：US20120297396A1

公开(公告)日：2012-11-22

申请号：US13475739

申请日：2012-05-18

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/50

CPC classification number: G06F9/5077 ,  G06F9/3012 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/46 ,  G06F9/4881 ,  G06F9/52 ,  G06F13/4068 ,  G06F15/80

Abstract: A global interconnect system. The global interconnect system includes a plurality of resources having data for supporting the execution of multiple code sequences and a plurality of engines for implementing the execution of the multiple code sequences. A plurality of resource consumers are within each of the plurality of engines. A global interconnect structure is coupled to the plurality of resource consumers and coupled to the plurality of resources to enable data access and execution of the multiple code sequences, wherein the resource consumers access the resources through a per cycle utilization of the global interconnect structure.

Abstract translation: 全球互连系统。 全局互连系统包括具有用于支持多个代码序列的执行的数据的多个资源和用于实现多个代码序列的执行的多个引擎。 多个资源消耗者在多个发动机的每一个内。 全局互连结构耦合到多个资源使用者，并耦合到多个资源，以实现多个代码序列的数据访问和执行，其中资源使用者通过全局互连结构的每周期利用来访问资源。

公开(公告)号：US20120297170A1

公开(公告)日：2012-11-22

申请号：US13475708

申请日：2012-05-18

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/30

CPC classification number: G06F9/3005 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/5005 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/4068

Abstract: A method for decentralized resource allocation in an integrated circuit. The method includes receiving a plurality of requests from a plurality of resource consumers of a plurality of partitionable engines to access a plurality resources, wherein the resources are spread across the plurality of engines and are accessed via a global interconnect structure. At each resource, a number of requests for access to said each resource are added. At said each resource, the number of requests are compared against a threshold limiter. At said each resource, a subsequent request that is received that exceeds the threshold limiter is canceled. Subsequently, requests that are not canceled within a current clock cycle are implemented.

Abstract translation: 一种集成电路中分散资源分配的方法。 该方法包括从多个可分割引擎的多个资源使用者接收多个请求以访问多个资源，其中资源分布在多个引擎上并经由全局互连结构访问。 在每个资源处，添加对所述每个资源的访问的多个请求。 在所述每个资源中，将请求数与阈值限制器进行比较。 在所述每个资源处，接收到的超过阈值限制器的后续请求被取消。 随后，实现在当前时钟周期内未被取消的请求。