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公开(公告)号：US10191453B2
公开(公告)日：2019-01-29
申请号：US15041202
申请日：2016-02-11
Applicant: NXP B.V.
Inventor： Nenad Pavlovic , Vladislav Dyachenko , Tarik Saric
IPC: G04F10/00 , H03C3/09 , H03L7/197 , H03L7/085 , H03L7/099 , H03M1/38 , G01S7/02 , G01S7/35 , G01S13/32 , G01S13/00
Abstract: A time to digital converter may include a synchronization block configured to output a voltage pulse with duration based on a time difference between a reference oscillating signal and an input oscillating signal; a charge pump arranged to receive the voltage pulse and to convert the voltage pulse into a current pulse; an integrator comprising an integrator capacitor, the integrator being configured to receive the current pulse and integrate the current pulse as a charge on the integrator capacitor, resulting in an integrator output voltage; and a successive approximation register configured to determine the integrator output voltage with respect to a reference voltage by adjusting the charge on the integrator capacitor so as to reduce the integrator output voltage to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage as a digital signal.
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公开(公告)号：US10439555B2
公开(公告)日：2019-10-08
申请号：US15832857
申请日：2017-12-06
Applicant: NXP B.V.
Inventor： Tarik Saric , Juan Felipe Osorio Tamayo
Abstract: A chirp-generator comprising a phase-detector for providing a phase-difference-signal representative of a phase difference between a clock-input-signal and a feedback-signal. A VCO-circuit is configured to provide a chirp-generator-output-signal based on the phase-difference-signal. The VCO-circuit comprises a switched-varactor-bank, which includes a plurality of varactors, and a varactor-switch associated with each of the plurality of varactors. The varactor-switch is configured to selectively control whether or not the associated varactor contributes to the capacitance of the VCO-circuit, based on the state of a varactor-control-signal. The chirp-generator also includes a feedback-component configured to: receive the chirp-generator-output-signal; and apply a variable-multiplication-factor to the chirp-generator-output-signal in order to provide the feedback signal for the phase-detector. A controller provides a sequence of different variable-multiplication-factors to the feedback-component; and provides varactor-control-signals to the plurality of varactors such that the varactors are sequentially controlled such that they contribute to the capacitance of the VCO-circuit.
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公开(公告)号：US20180191302A1
公开(公告)日：2018-07-05
申请号：US15832857
申请日：2017-12-06
Applicant: NXP B.V.
Inventor： Tarik Saric , Juan Felipe Osorio Tamayo
CPC classification number: H03B5/1243 , G01S7/032 , G01S7/35 , G01S13/343 , H03B5/1212 , H03B5/1262 , H03B5/1265 , H03C3/0925 , H03C3/0941 , H03C3/0958 , H03L7/099 , H03L7/197 , H03L2207/06
Abstract: A chirp-generator comprising a phase-detector for providing a phase-difference-signal representative of a phase difference between a clock-input-signal and a feedback-signal. A VCO-circuit is configured to provide a chirp-generator-output-signal based on the phase-difference-signal. The VCO-circuit comprises a switched-varactor-bank, which includes a plurality of varactors, and a varactor-switch associated with each of the plurality of varactors. The varactor-switch is configured to selectively control whether or not the associated varactor contributes to the capacitance of the VCO-circuit, based on the state of a varactor-control-signal. The chirp-generator also includes a feedback-component configured to: receive the chirp-generator-output-signal; and apply a variable-multiplication-factor to the chirp-generator-output-signal in order to provide the feedback signal for the phase-detector. A controller provides a sequence of different variable-multiplication-factors to the feedback-component; and provides varactor-control-signals to the plurality of varactors such that the varactors are sequentially controlled such that they contribute to the capacitance of the VCO-circuit.
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公开(公告)号：US09584177B2
公开(公告)日：2017-02-28
申请号：US15041217
申请日：2016-02-11
Applicant: NXP B.V.
Inventor： Nenad Pavlovic , Vladislav Dyachenko , Tarik Saric
IPC: H04L1/00 , H04B1/7073 , H03L7/197 , H04B1/69 , H03C3/09
CPC classification number: H04B1/7073 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0958 , H03C3/0991 , H03L7/1976 , H04B2001/6912 , H04B2201/7073
Abstract: A phase locked loop is disclosed having a frequency controlled oscillator, a feedback path, a time to digital converter and a memory. The frequency controlled oscillator comprises a first control input for varying the frequency of the output of the frequency controlled oscillator so as to track a reference frequency and a second control input for modulating the frequency of the output signal so as to produce a chirp. The feedback path is configured to provide an input signal to the time to digital converter, and comprises modulation cancelling module operable to remove the frequency modulation resulting from the second control input from the output signal. The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input. The phase locked loop is operable in a chirp mode, in which the second control input is produced by determining a value for the second control input corresponding with a desired chirp frequency based on the stored second control input values in the memory, and in which the phase locked loop is configured to determine the first control input based on the feedback path from which the modulation cancelling module has removed the frequency modulation resulting from the second control input.
Abstract translation: 公开了一种具有频率控制振荡器，反馈路径，时间到数字转换器和存储器的锁相环。 频率控制振荡器包括用于改变频率控制振荡器的输出频率以跟踪参考频率的第一控制输入和用于调制输出信号的频率以产生啁啾的第二控制输入。 反馈路径被配置为向时间到数字转换器提供输入信号，并且包括调制解除模块，其可操作以从输出信号中去除由第二控制输入产生的频率调制。 存储器存储每个对应于期望啁啾频率并且补偿频率控制振荡器对第二控制输入的响应中的非线性的第二控制输入值。 锁相环可以在啁啾模式下操作，其中通过基于存储器中存储的第二控制输入值确定与期望啁啾频率对应的第二控制输入的值来产生第二控制输入，其中， 锁相环被配置为基于调制消除模块从其中移除由第二控制输入产生的频率调制的反馈路径来确定第一控制输入。
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公开(公告)号：US20240159888A1
公开(公告)日：2024-05-16
申请号：US18498138
申请日：2023-10-31
Applicant: NXP B.V.
Inventor： Robert Rutten , Andries Pieter Hekstra , Salvatore Drago , Tarik Saric
CPC classification number: G01S13/584 , G01S7/354 , G01S7/356 , G01S13/931
Abstract: A radar sensor comprising a chirp generator that is configured to provide radar signalling for transmission. The radar signalling comprises a sequence of radar chirps, and wherein each radar chirp has a chirp slope that defines the rate of change of frequency in the radar chirp. A mixer multiplies the transmitted radar signalling with a received, reflected version of the transmitted radar signalling in order to provide analogue intermediate frequency, IF, signalling. An ADC samples the IF signalling in order to generate digital signalling. A digital processor populates a 2-dimensional array of bin-values based on the digital-values, such that: a first axis of the 2-dimensional array is a fast time axis and a second axis of the 2-dimensional array is a slow time axis. A chirp slope frequency adjuster sets the chirp slope of the radar chirps based on an index in the sequence of radar chirps. The digital processor performs DFT calculations on the bin-values in the 2-dimensional array along the fast time axis and the slow time axis in order to determine the range and velocity of any detected objects.
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Patent Agency Ranking
公开(公告)号：US20230417872A1
公开(公告)日：2023-12-28
申请号：US17846755
申请日：2022-06-22
Applicant: NXP B.V.
Inventor： Piotr Gibas , Tarik Saric
CPC classification number: G01S7/4056 , H03L7/099 , G01S7/4004
Abstract: A radar system injects a calibrated current at a signal generator during a reset portion and acquisition portion of each chirp period. The signal generator employs “gear-switching” to reduce PLL bandwidth during an acquisition phase and to increase the phase lock loop (PLL) bandwidth during a reset phase. By employing gear switching to change the bandwidth of the PLL circuit during the different portions of each chirp period, the length of the reset period is reduced, thus improving overall efficiency of the radar system while maintaining good performance.
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公开(公告)号：US11228318B1
公开(公告)日：2022-01-18
申请号：US17083968
申请日：2020-10-29
Applicant: NXP B.V.
Inventor： Tarik Saric , Piotr Gibas , Zhirui Zong
Abstract: Exemplary aspects of the present disclosure involve a system and related method of PLL circuitry in a chirp signaling FMCW system having a variable PLL bandwidth (BW). To adjust the BW, the PLL circuitry may provide for variable capacitance in the circuitry. This capacitance change may allow for a bandwidth for one slope, as used for the acquisition period. The capacitance may then be adjusted to allow for a different bandwidth for another slope which is used to reset the circuitry in preparation for another frequency sweep. Adjusting the PLL BW, via variable capacitance, may be used to mitigate phase noise which can adversely the PLL.
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公开(公告)号：US20210026002A1
公开(公告)日：2021-01-28
申请号：US16521120
申请日：2019-07-24
Applicant: NXP B.V.
Abstract: Aspects of the present disclosure are directed to injection locking and related apparatuses. As may be implemented in accordance with one or more embodiments, an apparatus includes a plurality of injection-locking circuits configured to receive an injection signal, each injection-locking circuit including a mixer and a lock-detection circuit. In each of the injection-locking circuits, the lock-detection circuit detects a lock-status relationship between the injection signal and a signal output from the injection-locking circuit. In response to the lock-status relationship indicating an unlocked condition, a phase/magnitude of the injection signal is adjusted. In response to the lock-status relationship indicating a locked condition, transmission of an FM continuous wave (FMCW) chirp signal is facilitated.
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公开(公告)号：US10284209B2
公开(公告)日：2019-05-07
申请号：US15987670
申请日：2018-05-23
Applicant: NXP B.V.
Inventor： Tarik Saric
Abstract: A phase locked loop for generating a frequency chirp is disclosed. The phase locked loop comprises a phase frequency detector configured to receive a reference frequency signal at a first input, a low pass filter configured to receive a current from the phase frequency detector at a filter input, and to output a control voltage, a voltage controlled oscillator configured to generate the frequency chirp at an output in response to receiving the control voltage, a feedback path connecting the output of the voltage controlled oscillator to a second input of the phase frequency detector, the feedback path comprising a frequency divider; and a timing module configured to generate a reset pulse. The low pass filter comprises a plurality of capacitors connected in parallel between the filter input and a common voltage line; and a voltage source configured to generate an initial control voltage. The voltage source is switchably connected to a node between a first capacitor of the plurality of capacitors and the common voltage line, and is connected to the node during a chirp reset mode defined by the reset pulse such that the voltage at the node is substantially equalized to the initial control voltage.
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公开(公告)号：US20160373122A1
公开(公告)日：2016-12-22
申请号：US15170624
申请日：2016-06-01
Applicant: NXP B.V.
Inventor： Tarik Saric , Juan Felipe Osorio Tamayo
CPC classification number: H03L7/107 , G01S7/032 , G01S13/343 , G01S13/345 , G01S13/931 , H03B23/00 , H03L7/0891 , H03L7/093 , H03L7/099 , H03L7/1974 , H03L7/1976
Abstract: A frequency synthesizer circuit for a car radar system is disclosed, the circuit comprising: a phase locked loop for providing a frequency chirp at a range of tuning voltages, said phase locked loop comprising: a phase detector and a voltage controlled oscillator, wherein said phase locked loop has an open loop gain dependent on the tuning voltage and a gain of the voltage controlled oscillator; a first varactor unit for altering the gain of the voltage controlled oscillator over a first subset range of tuning voltages; and a second varactor unit for altering the gain of the voltage controlled oscillator over a second subset range of tuning voltages, wherein the second subset range of tuning voltages is higher than the first subset range of tuning voltages; such that variations in the open loop gain over the first and second subset range of tuning voltages of the range of tuning voltages are compensated for by the varactor units.
Abstract translation: 公开了一种用于汽车雷达系统的频率合成器电路，该电路包括：用于在调谐电压范围内提供频率啁啾的锁相环，所述锁相环包括：相位检测器和压控振荡器，其中所述相位 锁定环路具有取决于调谐电压和压控振荡器的增益的开环增益; 第一变容二极管单元，用于在第一子调谐电压范围内改变压控振荡器的增益; 以及第二变容二极管单元，用于在第二子调谐电压范围内改变压控振荡器的增益，其中调谐电压的第二子范围高于调谐电压的第一子集范围; 使得在调谐电压范围内的调谐电压的第一和第二子集范围内的开环增益的变化由变容二极管单元补偿。
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