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    IMAGE SENSOR WITH THREE READOUT APPROACH FOR PHASE DETECTION AUTOFOCUS AND IMAGE SENSING PIXELS
    1.
    发明申请
    IMAGE SENSOR WITH THREE READOUT APPROACH FOR PHASE DETECTION AUTOFOCUS AND IMAGE SENSING PIXELS 有权

    公开(公告)号：US20220394201A1

    公开(公告)日：2022-12-08

    申请号：US17342383

    申请日：2021-06-08

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Chengcheng Xu ,  Rui Wang ,  Wei Deng ,  Chun-Sheng Yang ,  Xueqing Wang

    IPC: H04N5/378 ,  H04N5/3745 ,  H01L27/146 ,  H01L27/148

    Abstract: An imaging device includes a plurality of photodiodes arranged in a photodiode array to generate charge in response to incident light. The plurality of photodiodes includes first and second photodiodes. A shared floating diffusion receives charge transferred from the first and second photodiodes. An analog to digital converter (ADC) performs a first ADC conversion to generate a reference readout in response to charge in the shared floating diffusion after a reset operation. The ADC is next performs a second ADC conversion to generate a first half of a phase detection autofocus (PDAF) readout in response to charge transferred from the first photodiode to the shared floating diffusion. The ADC then performs a third ADC conversion to generate a full image readout in response to charge transferred from the second photodiode combined with the charge transferred previously from the first photodiode in the shared floating diffusion.

    Image sensor with voltage supply grid clamping
    2.
    发明授权
    Image sensor with voltage supply grid clamping 有权

    公开(公告)号：US11218659B2

    公开(公告)日：2022-01-04

    申请号：US16708135

    申请日：2019-12-09

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Chengcheng Xu ,  Rui Wang ,  Bi Yuan ,  Liang Zuo

    IPC: H04N5/378 ,  H04N5/3745 ,  H04N5/374 ,  H04N5/376 ,  H04N5/369 ,  H04N5/351

    Abstract: An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.

    Comparator first stage clamp
    4.
    发明授权
    Comparator first stage clamp 有权

    公开(公告)号：US11381771B1

    公开(公告)日：2022-07-05

    申请号：US17127524

    申请日：2020-12-18

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Hiroaki Ebihara ,  Chengcheng Xu

    IPC: H04N5/369 ,  H04N5/378 ,  H03K5/24

    Abstract: A comparator includes a first stage including a first output to generate a first output signal that transitions between an upper and lower voltage level in response to a comparison of first and second inputs of the first stage. A second stage includes an input coupled to receive the first output signal from the first output of the first stage, and a second output configured to generate a second output signal in response to the first output signal. A clamp circuit includes a first node and a second node. The first node is coupled to the first output of the first stage and the second node is coupled to a supply voltage. The clamp circuit is configured to clamp a voltage difference between the first node and the second node to clamp a voltage swing of the first output signal.

    PHASE DETECTION AUTO FOCUS WITH HORIZONTAL/VERTICAL QUAD PHASE DETECTION
    5.
    发明公开
    PHASE DETECTION AUTO FOCUS WITH HORIZONTAL/VERTICAL QUAD PHASE DETECTION 审中-公开

    公开(公告)号：US20240334085A1

    公开(公告)日：2024-10-03

    申请号：US18295207

    申请日：2023-04-03

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Rui Wang ,  Chengcheng Xu ,  Lihang Fan ,  Eiichi Funatsu

    IPC: H04N25/704 ,  G02B5/20 ,  H04N25/13 ,  H04N25/44 ,  H04N25/78

    CPC classification number: H04N25/704 ,  G02B5/201 ,  H04N25/134 ,  H04N25/44 ,  H04N25/78

    Abstract: An imaging device includes a pixel array with 2×2 pixel circuits arranged in rows and columns. Each 2×2 pixel circuit includes 4 photodiodes. Bitlines are coupled to the 2×2 pixel circuits and a color filter array is disposed over photodiodes of the pixel array. The color filter array includes color filters having a first color, color filters having a second color, color filters having a third color. The photodiodes of each 2×2 pixel circuits are covered by one of the color filters. Photodiodes covered by color filters having the first color and photodiodes covered by color filters having the second color are configured to provide non-phase detection (non-PD) information. Photodiodes covered by color filters having the third color are configured to provide phase detection (PD) information. Half of the 2×2 pixel circuits have the photodiodes covered by color filters having the third color.

    COMPARATOR FIRST STAGE CLAMP
    7.
    发明申请
    COMPARATOR FIRST STAGE CLAMP 有权

    公开(公告)号：US20220201231A1

    公开(公告)日：2022-06-23

    申请号：US17127524

    申请日：2020-12-18

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Hiroaki Ebihara ,  Chengcheng Xu

    IPC: H04N5/378 ,  H03K5/24

    Abstract: A comparator includes a first stage including a first output to generate a first output signal that transitions between an upper and lower voltage level in response to a comparison of first and second inputs of the first stage. A second stage includes an input coupled to receive the first output signal from the first output of the first stage, and a second output configured to generate a second output signal in response to the first output signal. A clamp circuit includes a first node and a second node. The first node is coupled to the first output of the first stage and the second node is coupled to a supply voltage. The clamp circuit is configured to clamp a voltage difference between the first node and the second node to clamp a voltage swing of the first output signal.

    Dynamic current control for column ADC
    8.
    发明授权
    Dynamic current control for column ADC 有权

    公开(公告)号：US12199632B2

    公开(公告)日：2025-01-14

    申请号：US18176373

    申请日：2023-02-28

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Hiroaki Ebihara ,  Chengcheng Xu ,  Satoshi Sakurai ,  Kenny Geng

    IPC: H03M1/46

    Abstract: A tail current source of a comparator includes a first transistor and a second transistor configured to operate as current sources, wherein the first and second transistors are coupled between a tail node of the comparator and a voltage node, and wherein the tail comprises a node coupled to first and second inputs of the comparator. The tail current source also includes a switch configured to selectively couple the second transistor between the tail and the voltage node, and a bias voltage source coupled to gates of the first and second transistors. The switch is configured to be on during an analog-to-digital conversion (ADC) reset signal period and an ADC image signal period, and the switch is configured to be off during an auto-zero period, a period between the ADC reset signal and image signal periods, and a period after the ADC image signal period.

    PIXEL DESIGNS WITH REDUCED LOFIC RESET AND SETTLING TIMES
    9.
    发明公开
    PIXEL DESIGNS WITH REDUCED LOFIC RESET AND SETTLING TIMES 审中-公开

    公开(公告)号：US20230421922A1

    公开(公告)日：2023-12-28

    申请号：US17849403

    申请日：2022-06-24

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Zhe Gao ,  Chengcheng Xu ,  Dennis Tunglin Lee ,  Tiejun Dai

    IPC: H04N5/378 ,  H04N5/355 ,  H01L27/146

    CPC classification number: H04N5/378 ,  H04N5/3559 ,  H01L27/14643 ,  H01L27/14612

    Abstract: Pixel designs with reduced LOFIC reset and settling times are disclosed herein. In one embodiment, a pixel cell includes a photosensor configured to photogenerate image charge in response to incident light, a floating diffusion to receive the image charge from the photosensor, a transfer transistor coupled between the floating diffusion and the photosensor to transfer the image charge to the floating diffusion, and a first reset transistor coupled between the floating diffusion and the voltage supply. The pixel cell further includes a capacitor having two ends, and a second reset transistor. A first end of the capacitor is coupled to the floating diffusion. The second reset transistor is coupled between a second end of the capacitor and the voltage supply.

    Image sensor with three readout approach for phase detection autofocus and image sensing photodiodes through multiple column bitlines
    10.
    发明授权
    Image sensor with three readout approach for phase detection autofocus and image sensing photodiodes through multiple column bitlines 有权

    公开(公告)号：US11463648B1

    公开(公告)日：2022-10-04

    申请号：US17342375

    申请日：2021-06-08

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Chengcheng Xu ,  Rui Wang ,  Wei Deng ,  Chun-Sheng Yang ,  Xueqing Wang

    IPC: H04N5/378 ,  H04N5/232 ,  H04N5/374 ,  H04N5/369

    Abstract: An imaging device includes a photodiode array with a first and second photodiodes. First and second floating diffusions are configured to receive charge from the first and second photodiodes, respectively. An analog to digital converter (ADC) is configured to receive simultaneously first and second bitline signals from the first and second floating diffusions, respectively. The ADC is configured to generate a reference readout in response to the first and second bitline signals after a reset operation. The ADC next generates a first half of a phase detection autofocus (PDAF) readout in response to the first and second bitline signals after charge is transferred from the first PDAF photodiode to the first floating diffusion. The ADC then generates a full image readout in response to the first and second bitline signals after charge is transferred from the second photodiode to the second floating diffusion.

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