公开(公告)号：US20210357014A1

公开(公告)日：2021-11-18

申请号：US17388830

申请日：2021-07-29

Applicant: Oracle International Corporation

Inventor： Lin Zhang ,  Yifan YangGong ,  Sebastian Turullols

IPC: G06F1/28 ,  G06F1/08

Abstract: A method for determining power dissipation within a computer system is disclosed. A circuit block may receive a regulated voltage level on a power supply signal generated by a voltage regulator circuit. A power control circuit may measure a current drawn by the circuit block, and determine a real-time voltage level for the power supply signal using the current and based on a slope value and a zero-load voltage level. Additionally, power control circuit may determine a power dissipation for the circuit block using the current and the real-time voltage level, and adjust an operation parameter of the circuit block based on the power dissipation.

公开(公告)号：US20190332156A1

公开(公告)日：2019-10-31

申请号：US15965765

申请日：2018-04-27

Applicant: Oracle International Corporation

Inventor： Yufei Qian ,  Yifan YangGong ,  Sebastian Turullols

IPC: G06F1/32

Abstract: A method for adjusting operation parameters of a computer system based on power consumption of the computer system is disclosed. During a power state transition of the computer system, a voltage level of a power supply signal may be sampled at a plurality of time points to generate a multiple voltage level samples. A voltage level of a selected one of the multiple voltage level samples may be adjusted using a particular coefficient of multiple coefficients to generate an updated voltage level sample. A power consumption of the computer system may be determined using the updated voltage level sample, and based on the power consumption, at least one operation parameter of the computer system may be adjusted.

公开(公告)号：US09772375B2

公开(公告)日：2017-09-26

申请号：US14691332

申请日：2015-04-20

Applicant: Oracle International Corporation

Inventor： Sebastian Turullols ,  Vijay Srinivasan ,  Changku Hwang

IPC: G01R31/317 ,  G06F1/32 ,  H03K3/037 ,  H03K5/159 ,  G01R31/30 ,  H03K5/133

CPC classification number: G01R31/31725 ,  G01R31/3004 ,  G01R31/31937 ,  G06F1/3206 ,  G06F1/3296 ,  H03K3/037 ,  H03K5/133 ,  H03K5/159

Abstract: Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilize a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. In one embodiment, the digital sampling circuit or digital voltage monitor circuit includes a coarse delay component or circuit that further delays the propagation of a clock signal through the delay line. The coarse delay circuit may be programmed to delay the propagation of the signal through the delay line in such a manner as to allow for multiple edges of a clock or test signal to travel simultaneously down the delay line and increase the sensitivity of the circuit. Additional sensitivity of the digital voltage monitor circuit may also be obtained through selection of the types of components that comprise the circuit and a clock jitter monitor circuit configured with a constant supply voltage.

公开(公告)号：US20160061667A1

公开(公告)日：2016-03-03

申请号：US14524392

申请日：2014-10-27

Applicant: Oracle International Corporation

Inventor： Changku Hwang ,  Ha Pham ,  Daisy Jian ,  Sebastian Turullols

IPC: G01K7/00 ,  G01R19/10 ,  G01R19/25

CPC classification number: G01K7/00 ,  G01K7/01 ,  G01K2219/00 ,  G01R19/10 ,  G01R19/2506

Abstract: Embodiments of a temperature sensing apparatus are disclosed. The apparatus may include a voltage generator and circuitry. The voltage generator may generate a first voltage level and a second voltage level dependent on an operating temperature. In response to a given change in the operating temperature, the first and second voltage levels may change, with the second voltage level changing by a different amount than the first voltage level. The voltage generator may generate a third voltage level. The circuitry may measure the first voltage level, the second voltage level, and the third voltage level, and may calculate the operating temperature dependent on a ratio of a difference between the first voltage level and the second voltage level and the third voltage level.

Abstract translation: 公开了一种温度检测装置的实施例。 该装置可以包括电压发生器和电路。 电压发生器可以产生取决于工作温度的第一电压电平和第二电压电平。 响应于工作温度的给定变化，第一和第二电压电平可以改变，其中第二电压电平改变与第一电压电平不同的量。 电压发生器可产生第三电压电平。 电路可以测量第一电压电平，第二电压电平和第三电压电平，并且可以根据第一电压电平和第二电压电平和第三电压电平之间的差的比来计算工作温度。

公开(公告)号：US20160048187A1

公开(公告)日：2016-02-18

申请号：US14461042

申请日：2014-08-15

Applicant: Oracle International Corporation

Inventor： Haowei Zhang ,  Xiaoying Shen ,  Sebastian Turullols ,  Robert T. Golla

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3287 ,  G06F9/3869 ,  Y02D10/171

Abstract: Embodiments of the invention provide adaptive power ramp control (APRC) in microprocessors. One implementation of the APRC can compute a present core power and a present power ramp condition in the microprocessor, for example, to determine whether the present power is in a particular predefined control zone and whether the present power ramp is greater than a predefined threshold for that control zone. Those determinations can indicate a likelihood of an imminent, undesirable power ramp condition and can inform entry into a control mode. The APRC can generate an appropriate stall control signal in response to its present control mode, and the stall control signal can stall operation of at least one functional unit of the microprocessor according to a predefined stall pattern. This can effectively combat the imminent power ramp condition by reducing the power usage of the microprocessor.

Abstract translation: 本发明的实施例在微处理器中提供自适应功率斜坡控制（APRC）。 APRC的一个实施方案可以计算微处理器中的当前核心功率和当前的功率斜坡状态，例如，以确定当前功率是否在特定的预定义控制区以及当前功率斜坡是否大于 那个控制区。 这些确定可以指示即将发生的不期望的功率斜坡状况的可能性，并且可以通知进入控制模式。 APRC可以响应于其当前控制模式而产生适当的失速控制信号，并且失速控制信号可以根据预定的失速模式停止微处理器的至少一个功能单元的操作。 这可以通过减少微处理器的功率消耗来有效地抵抗迫在眉睫的功率斜坡状况。

公开(公告)号：US20140354264A1

公开(公告)日：2014-12-04

申请号：US13903445

申请日：2013-05-28

Applicant: Oracle International Corporation

Inventor： Sebastian Turullols

IPC: G01R19/25 ,  G01R31/28

CPC classification number: G01R19/2503 ,  G01R31/31721

Abstract: Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilizes a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. The digitized samples are routed to either an on-die memory structure for later analysis or are transmitted to one or more pins of a chip for capture and analysis by an external analyzer.

Abstract translation: 本公开的实现涉及用于通过数字采样电路测量集成电路的片上电压电平的系统和/或方法。 特别地，系统和/或方法利用基于延迟线的模数 - 数字采样电路，其产生随时间的电压读数，例如在每个高频时钟周期。 数字化样本被路由到片上存储器结构以供稍后分析，或者被传输到芯片的一个或多个引脚以由外部分析器捕获和分析。

公开(公告)号：US11899513B2

公开(公告)日：2024-02-13

申请号：US18151883

申请日：2023-01-09

Applicant: Oracle International Corporation

Inventor： Yifan YangGong ,  Sebastian Turullols

IPC: G06F1/32 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3234

CPC classification number: G06F1/206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296

Abstract: A power management controller is disclosed. Broadly speaking, the controller may, in response to receiving a timing signal, monitor a temperature of an integrated circuit including multiple processor clusters. The controller may generate a comparison of the temperature and a threshold value, and in response to a determination that the comparison indicates that the temperature is less than the threshold value, transition a particular processor cluster to a new power state.

公开(公告)号：US10884472B2

公开(公告)日：2021-01-05

申请号：US15965765

申请日：2018-04-27

Applicant: Oracle International Corporation

Inventor： Yufei Qian ,  Yifan YangGong ,  Sebastian Turullols

IPC: G06F1/3206 ,  G06F1/324

Abstract: A method for adjusting operation parameters of a computer system based on power consumption of the computer system is disclosed. During a power state transition of the computer system, a voltage level of a power supply signal may be sampled at a plurality of time points to generate a multiple voltage level samples. A voltage level of a selected one of the multiple voltage level samples may be adjusted using a particular coefficient of multiple coefficients to generate an updated voltage level sample. A power consumption of the computer system may be determined using the updated voltage level sample, and based on the power consumption, at least one operation parameter of the computer system may be adjusted.

公开(公告)号：US10656700B2

公开(公告)日：2020-05-19

申请号：US15645528

申请日：2017-07-10

Applicant: Oracle International Corporation

Inventor： Yifan YangGong ,  Sebastian Turullols

IPC: G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/20

Abstract: A power management controller is disclosed. Broadly speaking, the controller may, in response to detecting a timing signal, determine a total power consumption for a plurality of processor clusters, each of which includes a plurality of processor cores. The controller may determine a performance metric using the total power consumption and compare the performance metric to a limit. Based on a result of the comparison, the controller may select a new power state for at least one of the processor clusters.

公开(公告)号：US20190339137A1

公开(公告)日：2019-11-07

申请号：US16459464

申请日：2019-07-01

Applicant: Oracle International Corporation

Inventor： Venkatram Krishnaswamy ,  Sebastian Turullols

IPC: G01K15/00

Abstract: A system is disclosed, including an interface to a DUT and a testing apparatus. The DUT includes a first plurality of temperature sensing circuits. The testing apparatus may store a plurality of control values. Each control value may depend on at least two calibration values of corresponding temperature sensing circuits of a second plurality of temperature sensing circuits. The testing apparatus may generate a plurality of calibration values for the DUT. Each calibration value corresponds to one of the first plurality of temperature sensing circuits. The testing apparatus may determine a plurality of test values for the DUT. The testing apparatus may calculate a probability value, and repeat generation of the plurality of calibration values upon determining that the probability value is less than a predetermined threshold value. The probability value corresponds to a likelihood that the plurality of calibration values is accurate.