公开(公告)号：US20220365580A1

公开(公告)日：2022-11-17

申请号：US17322402

申请日：2021-05-17

Applicant: QUALCOMM INCORPORATED

Inventor： VIJAYAKUMAR ASHOK DIBBAD ,  Bharat Kumar RANGARAJAN ,  Dipti Ranjan PAL ,  Keith Alan BOWMAN ,  Matthew SEVERSON ,  Gordon LEE

IPC: G06F1/324 ,  G06F1/3296 ,  H02H9/02

Abstract: In controlling power in a portable computing device (“PCD”), a power supply input to a PCD subsystem may be modulated with a modulation signal when an over-current condition is detected. Detection of the modulation signal may indicate to a processing core of the subsystem to reduce its processing load. Compensation for the modulation signal in the power supply input may be applied so that the processing core is essentially unaffected by the modulation signal.

公开(公告)号：US20220137687A1

公开(公告)日：2022-05-05

申请号：US17085505

申请日：2020-10-30

Applicant: QUALCOMM INCORPORATED

Inventor： Christopher Kong Yee CHUN ,  Chandan AGARWALLA ,  Dipti Ranjan PAL ,  Kumar Kanti GHOSH ,  Matthew SEVERSON ,  Nilanjan BANERJEE ,  Joshua STUBBS

IPC: G06F1/26

Abstract: Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.

公开(公告)号：US20190339757A1

公开(公告)日：2019-11-07

申请号：US15967872

申请日：2018-05-01

Applicant: QUALCOMM Incorporated

Inventor： Abinash ROY ,  Dipti Ranjan PAL ,  Avinash GADDE

IPC: G06F1/26

Abstract: Methods and apparatuses to power up multiple load circuits are presented. The apparatus includes a power delivery network, multiple load circuits configured to be powered via the power delivery network, and a wakeup control circuit configured to power up the multiple load circuits at a frequency based on a resonance frequency of the power delivery network. The method includes delivering power to the multiple load circuits by a power source via a power delivery network and powering up the multiple load circuits at a frequency, by a wakeup control circuit, based on a resonance frequency of the power delivery network.

公开(公告)号：US20250052812A1

公开(公告)日：2025-02-13

申请号：US18447446

申请日：2023-08-10

Applicant: QUALCOMM Incorporated

Inventor： Amit ANEJA ,  Dipti Ranjan PAL ,  Kiran Kumar MALIPEDDI

IPC: G01R31/317

Abstract: Methods and apparatuses directed to. In some examples, a die package includes voltage logic that provides a voltage to a voltage rail, clock logic that generates a clock signal, and adaptive clock distribution logic that receives the clock signal and the voltage. The adaptive clock distribution logic can increment an event count when the clock signal is above a threshold frequency, or when the voltage is below a threshold voltage level. The die package also includes a processor that can monitor the event counts during operation and determine a status of the adaptive clock distribution logic based on the event counts. In some examples, the processor can test the adaptive clock distribution logic by causing the clock signal to operate above the threshold frequency, or causing the voltage logic to provide the voltage below the threshold voltage level. The processor can then read the event counts to determine the status.

公开(公告)号：US20150295560A1

公开(公告)日：2015-10-15

申请号：US14251297

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Dipti Ranjan PAL ,  Paul Ivan PENZES ,  Wai Kit SIU

IPC: H03K3/012 ,  G11C19/34 ,  H03K3/037

CPC classification number: H03K3/012 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318594 ,  G11C19/34 ,  H03K3/0375

Abstract: A first apparatus includes at least one scan chain. Each of the at least one scan chain includes scan cells coupled together. Each scan cell in the at least one scan chain includes a first type of scan cell when a reset state of the scan cell is a first state, and a second type of scan cell when the reset state of the scan cell is a second state. One or more scan chains of the at least one scan chain includes at least one of the first type of scan cell and at least one of the second type of scan cell. A second apparatus includes first and second sets of scan chains including flip-flops without both set and reset functionality. Each of the flip-flops in the first and second sets of scan chains has a reset state of a first state and a second state, respectively.

Abstract translation: 第一装置包括至少一个扫描链。 所述至少一个扫描链中的每一个包括耦合在一起的扫描单元。 当扫描单元的复位状态是第一状态时，至少一个扫描链中的每个扫描单元包括第一类型的扫描单元，当扫描单元的复位状态是第二状态时，包括第二类型的扫描单元。 所述至少一个扫描链的一个或多个扫描链包括所述第一类型的扫描单元和所述第二类型的扫描单元中的至少一个。 第二装置包括第一和第二组扫描链，包括没有设置和复位功能的触发器。 第一组扫描链和第二组扫描链中的每个触发器分别具有第一状态和第二状态的复位状态。

公开(公告)号：US20230096760A1

公开(公告)日：2023-03-30

申请号：US17485361

申请日：2021-09-25

Applicant: QUALCOMM Incorporated

Inventor： Keith Alan BOWMAN ,  Daniel YINGLING ,  Dipti Ranjan PAL

IPC: H03K5/156 ,  H03L7/081 ,  H03K3/017

Abstract: Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock signal, determining a duty-cycle adjustment based on the measured one or more parameters, and adjusting a duty cycle of the clock signal based on the determined duty-cycle adjustment.

公开(公告)号：US20160091939A1

公开(公告)日：2016-03-31

申请号：US14497258

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Matthew Levi SEVERSON ,  Shih-Hsin Jason HU ,  Dipti Ranjan PAL ,  Madan KRISHNAPPA ,  Jeffrey GEMAR ,  Noman AHMED ,  Mohammad TAMJIDI ,  Mark KEMPFERT

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  G06F9/4405 ,  Y02D10/171

Abstract: A method for operating an electronic apparatus is provided. The method includes receiving a token, activating a power switch for powering up a core in response to the receiving the token, and outputting the token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. In one aspect, an electronic apparatus includes a power switch configured to power up to a core is provided. A power-switch control circuit is configured to receive a token, activate the power switch for powering up the core in response to receiving the token, output the received token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. A plurality of the power-switch control circuits is configured as a ring.

Abstract translation: 提供一种操作电子设备的方法。 该方法包括接收令牌，激活用于响应于接收到令牌的核心的电源开关，以及基于为核心加电的状态来输出令牌。 接收的令牌的输出被延迟直到达到核心的加电状态。 在一个方面，一种电子设备包括配置成提供电源至核心的电源开关。 功率开关控制电路被配置为接收令牌，激活电源开关以响应于接收到令牌来加电核心，基于为核心加电的状态输出接收到的令牌。 接收的令牌的输出被延迟直到达到核心的加电状态。 多个电源开关控制电路被配置为环。

公开(公告)号：US20210357502A1

公开(公告)日：2021-11-18

申请号：US16874538

申请日：2020-05-14

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar RANGARAJAN ,  Dipti Ranjan PAL ,  Keith Alan BOWMAN ,  Srinivas TURAGA ,  Ateesh Deepankar DE ,  Shih-Hsin Jason HU ,  Chandan AGARWALLA

IPC: G06F21/55 ,  G06F1/26

Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.

公开(公告)号：US20200264682A1

公开(公告)日：2020-08-20

申请号：US16276532

申请日：2019-02-14

Applicant: QUALCOMM Incorporated

Inventor： Dipti Ranjan PAL ,  Jeffrey GEMAR ,  Abinash ROY

IPC: G06F1/324 ,  G06F1/3237 ,  G06F1/08

Abstract: In certain aspects, an apparatus includes a first power chain, a second power chain, and an enable circuit having an output coupled to an input of the first power chain. The apparatus also includes a multiplexer having a first input coupled to an output of the first power chain, a second input coupled to the output of the enable circuit, and an output coupled to an input of the second power chain, wherein the multiplexer is configured to receive a select signal, and couple the first input or the second input to the output of the multiplexer based on the select signal.

公开(公告)号：US20190324512A1

公开(公告)日：2019-10-24

申请号：US16458940

申请日：2019-07-01

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward PODAIMA ,  Christophe Denis Bernard AVOINNE ,  Manokanthan SOMASUNDARAM ,  Sina DENA ,  Paul Christopher John WIERCIENSKI ,  Bohuslav RYCHLIK ,  Steven John HALTER ,  Jaya Prakash SUBRAMANIAM GANASAN ,  Myil RAMKUMAR ,  Dipti Ranjan PAL

IPC: G06F1/26 ,  G06F1/3287 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/10

Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.