公开(公告)号：US20170090508A1

公开(公告)日：2017-03-30

申请号：US14865092

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Shivam PRIYADARSHI ,  Anil KRISHNA ,  Raguram DAMODARAN ,  Jeffrey Todd BRIDGES ,  Thomas Philip SPEIER ,  Rodney Wayne SMITH ,  Keith Alan BOWMAN ,  David Joseph Winston HANSQUINE

IPC: G06F1/08 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F1/08 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3861 ,  G06F12/0804 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1024 ,  G06F2212/60 ,  Y02D10/126 ,  Y02D10/152

Abstract: The clock frequency of a processor is reduced in response to a dispatch stall due to a cache miss. In an embodiment, the processor clock frequency is reduced for a load instruction that causes a last level cache miss, provided that the load instruction is the oldest load instruction and the number of consecutive processor cycles in which there is a dispatch stall exceeds a threshold, and provided that the total number of processor cycles since the last level cache miss does not exceed some specified number.

公开(公告)号：US20220365580A1

公开(公告)日：2022-11-17

申请号：US17322402

申请日：2021-05-17

Applicant: QUALCOMM INCORPORATED

Inventor： VIJAYAKUMAR ASHOK DIBBAD ,  Bharat Kumar RANGARAJAN ,  Dipti Ranjan PAL ,  Keith Alan BOWMAN ,  Matthew SEVERSON ,  Gordon LEE

IPC: G06F1/324 ,  G06F1/3296 ,  H02H9/02

Abstract: In controlling power in a portable computing device (“PCD”), a power supply input to a PCD subsystem may be modulated with a modulation signal when an over-current condition is detected. Detection of the modulation signal may indicate to a processing core of the subsystem to reduce its processing load. Compensation for the modulation signal in the power supply input may be applied so that the processing core is essentially unaffected by the modulation signal.

公开(公告)号：US20250030407A1

公开(公告)日：2025-01-23

申请号：US18354374

申请日：2023-07-18

Applicant: QUALCOMM Incorporated

Inventor： Yimai PENG ,  Robert Joseph VACHON ,  Daniel YINGLING ,  Keith Alan BOWMAN

IPC: H03K3/037 ,  H03K17/00 ,  H03K19/21

Abstract: An apparatus, including: a clock gating circuit (CGC), including: a clock gating device configured to selectively gate/pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.

公开(公告)号：US20210399722A1

公开(公告)日：2021-12-23

申请号：US16906501

申请日：2020-06-19

Applicant: QUALCOMM Incorporated

Inventor： Fadi HAMDAN ,  Keith Alan BOWMAN ,  Nadeem ELEYAN ,  Xiang LI

IPC: H03K5/133 ,  H03L7/081

Abstract: Aspects of the disclosure are directed to adaptively delaying an input signal. In accordance with one aspect, an apparatus includes a plurality of delay units, wherein each of the plurality of delay units includes a substantially similar output load characteristic; a plurality of buffer units, wherein each of the plurality of buffer units is coupled to one of the plurality of delay units; wherein a quantity of the plurality of delay units equals a quantity of the plurality of buffer units; an additional delay unit coupled to a delay unit output of one of the plurality of delay units; and a one-hot decoder coupled to each of the plurality of buffer units, the one-hot decoder configured to enable one and only one of the plurality of buffer units.

公开(公告)号：US20230096760A1

公开(公告)日：2023-03-30

申请号：US17485361

申请日：2021-09-25

Applicant: QUALCOMM Incorporated

Inventor： Keith Alan BOWMAN ,  Daniel YINGLING ,  Dipti Ranjan PAL

IPC: H03K5/156 ,  H03L7/081 ,  H03K3/017

Abstract: Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock signal, determining a duty-cycle adjustment based on the measured one or more parameters, and adjusting a duty cycle of the clock signal based on the determined duty-cycle adjustment.

公开(公告)号：US20170300080A1

公开(公告)日：2017-10-19

申请号：US15133068

申请日：2016-04-19

Applicant: QUALCOMM Incorporated

Inventor： Palkesh JAIN ,  Virendra BANSAL ,  Manoj MEHROTRA ,  Keith Alan BOWMAN

IPC: G06F1/04 ,  G06F1/26 ,  H03K3/03 ,  H03L7/06

CPC classification number: G06F1/04 ,  G06F1/08 ,  G06F1/26 ,  G06F1/305 ,  H03K3/0315 ,  H03L7/06

Abstract: The present disclosure is directed to mitigating voltage droops. An aspect includes outputting, by a clock module coupled to a multiplexor, a first clock signal to the multiplexor, the first clock signal generated by a clock delay component of the clock module, receiving, by the clock module, a second clock signal from a phase-locked loop (PLL), wherein the PLL outputs a third clock signal to a processor coupled to the PLL and the multiplexor, selecting, by the multiplexor, the first clock signal to output to the processor based on detecting a droop in voltage on a power supply, and selecting, by the multiplexor, the third clock signal to output to the processor based on detecting that the droop in the voltage on the power supply has passed, wherein the clock module and the processor are coupled to the power supply.

公开(公告)号：US20170083031A1

公开(公告)日：2017-03-23

申请号：US14860717

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim ATALLAH ,  Hoan Huu NGUYEN ,  Keith Alan BOWMAN ,  Yeshwant Nagaraj KOLLA ,  Burt Lee PRICE ,  Samantak GANGOPADHYAY

IPC: G05F1/56

CPC classification number: G05F1/56 ,  H03K19/0008

Abstract: Systems and methods relate to a low-dropout voltage (LDO) voltage regulator which receives a maximum supply voltage and provides a regulated voltage to a load, where the load may be a processing core of a multi-core processing system. A leakage current supply source includes a leakage current sensor to determine a leakage current demand of the load of the LDO voltage regulator and a leakage current supply circuit to supply the leakage current demand. In this manner, the leakage current supply source provides current assistance to the LDO voltage regulator, such that the LDO voltage regulator can supply only dynamic current. Thus, headroom voltage of the LDO voltage regulator, which is a difference between the maximum supply voltage and the regulated voltage, can be reduced. Reducing the headroom voltage allows greater number of dynamic voltage and frequency scaling states of the load.

公开(公告)号：US20210357502A1

公开(公告)日：2021-11-18

申请号：US16874538

申请日：2020-05-14

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar RANGARAJAN ,  Dipti Ranjan PAL ,  Keith Alan BOWMAN ,  Srinivas TURAGA ,  Ateesh Deepankar DE ,  Shih-Hsin Jason HU ,  Chandan AGARWALLA

IPC: G06F21/55 ,  G06F1/26

Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.

公开(公告)号：US20210225435A1

公开(公告)日：2021-07-22

申请号：US17223764

申请日：2021-04-06

Applicant: Qualcomm Incorporated

Inventor： Hoan Huu NGUYEN ,  Francois Ibrahim ATALLAH ,  Keith Alan BOWMAN ,  Daniel YINGLING ,  Jihoon JEONG ,  Yu PU

IPC: G11C11/417 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/418 ,  G11C11/419

Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.

公开(公告)号：US20200098422A1

公开(公告)日：2020-03-26

申请号：US16138174

申请日：2018-09-21

Applicant: QUALCOMM Incorporated

Inventor： Hoan Huu NGUYEN ,  Francois Ibrahim ATALLAH ,  Keith Alan BOWMAN ,  Hari RAO

IPC: G11C11/419 ,  G11C11/4091 ,  G11C11/408 ,  G11C16/26 ,  G11C8/08 ,  G11C8/10 ,  G11C7/06

Abstract: Certain aspects of the present disclosure provide apparatus and methods for performing memory read operations. One example method generally includes precharging a plurality of memory columns during a precharging phase of a read access cycle. The method also includes sensing first data stored in a first memory cell of a first memory column of the plurality of memory columns during a memory read phase of the read access cycle, and sensing second data stored in a second memory cell of a second memory column of the plurality of memory columns during the same memory read phase of the read access cycle.