公开(公告)号：US20170085253A1

公开(公告)日：2017-03-23

申请号：US14861503

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Lipeng CAO ,  Jeffrey GEMAR ,  Ramaprasath VILANGUDIPITCHAI

IPC: H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/0372 ,  H03K3/356008 ,  H03K3/3562

Abstract: Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip-flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rail. The IC further includes a flip-flop and power multiplexing circuitry. The flip flop includes a master portion and a slave portion. The master portion is coupled to the first power rail for a regular operational mode and for a retention operational mode. The power multiplexing circuitry is configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode.

公开(公告)号：US20210255689A1

公开(公告)日：2021-08-19

申请号：US16790431

申请日：2020-02-13

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey GEMAR ,  Ambudhar TRIPATHI ,  Philippe MARTIN

IPC: G06F1/3228 ,  G06F1/04 ,  G06F1/3246 ,  G06F13/16 ,  G06F15/78

Abstract: In some aspects, the present disclosure provides a method for power management. The method includes receiving, by a power management unit (PMU), signaling indicative of a first plurality of latency durations from a first plurality of clients, each of the first plurality of latency durations corresponding to one of the first plurality of clients, wherein each of the first plurality of clients is configured to utilize a first shared resource for communication of data. In certain aspects, the method also includes selecting, by the PMU, a first latency duration from the first plurality of latency durations based on a determination that the first latency duration is the shortest latency duration of the first plurality of latency durations, and transitioning, by the PMU, the first shared resource from an active state to the first idle state.

公开(公告)号：US20200264682A1

公开(公告)日：2020-08-20

申请号：US16276532

申请日：2019-02-14

Applicant: QUALCOMM Incorporated

Inventor： Dipti Ranjan PAL ,  Jeffrey GEMAR ,  Abinash ROY

IPC: G06F1/324 ,  G06F1/3237 ,  G06F1/08

Abstract: In certain aspects, an apparatus includes a first power chain, a second power chain, and an enable circuit having an output coupled to an input of the first power chain. The apparatus also includes a multiplexer having a first input coupled to an output of the first power chain, a second input coupled to the output of the enable circuit, and an output coupled to an input of the second power chain, wherein the multiplexer is configured to receive a select signal, and couple the first input or the second input to the output of the multiplexer based on the select signal.

公开(公告)号：US20240425063A1

公开(公告)日：2024-12-26

申请号：US18338576

申请日：2023-06-21

Applicant: QUALCOMM INCORPORATED

Inventor： Vijayakumar Ashok DIBBAD ,  Jeffrey GEMAR ,  Shree Krishna PANDEY

IPC: B60W50/02 ,  B60W50/035 ,  B60W50/14

Abstract: Degradation of a power delivery network (PDN) in a computing device may be detected as part of a self-test during booting of the computing device or a device subsystem. The computing device may be an automotive vehicle control system. A clock signal provided to logic circuitry supplied by the PDN may be modulated, and the modulation frequency may be varied over a range. Voltage droop values in the logic circuitry may be measured in response to the modulation frequencies over the range. Impedance values may be determined by determining an odd harmonic of each of the voltage droop values. The impedance values may be compared with thresholds, and an alert or other indication may be issued if one or more of the impedance values exceeds a threshold.

公开(公告)号：US20160246362A1

公开(公告)日：2016-08-25

申请号：US15052786

申请日：2016-02-24

Applicant: QUALCOMM Incorporated

Inventor： Suresh SUGUMAR ,  Jeffrey GEMAR ,  Ali TAHA ,  Amy DERBYSHIRE ,  Tao XUE ,  Mohammad TAMJIDI ,  Rajat MITTAL

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3885 ,  Y02D10/152

Abstract: An apparatus includes a first circuit and a second circuit sharing an instruction stream. A voltage controller circuit is configured to provide an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream. In another aspect, a method of operating a power management function is presented. The method includes providing an instruction stream for a first circuit and a second circuit and providing selectively an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream.

Abstract translation: 一种装置包括第一电路和共享指令流的第二电路。 电压控制器电路被配置为响应于指令流的序列，独立于第一电路的电源电压而向第二电路提供操作电压和至少一个低功率电压。 另一方面，提出了一种操作电源管理功能的方法。 该方法包括提供用于第一电路和第二电路的指令流，并响应于指令序列而独立于第一电路的电源电压而选择性地向第二电路提供操作电压和至少一个低功率电压 流。

公开(公告)号：US20240264651A1

公开(公告)日：2024-08-08

申请号：US18166381

申请日：2023-02-08

Applicant: QUALCOMM Incorporated

Inventor： Vijayakumar Ashok DIBBAD ,  Nikhil Ashok BHELAVE ,  Jeffrey GEMAR ,  Matthew SEVERSON

IPC: G06F1/30

CPC classification number: G06F1/305

Abstract: Various embodiments include methods performed by a processor for managing voltage droop margins of a power distribution network (PDN). Various embodiments may include receiving, by a processor from a first client powered by a shared power rail within the PDN, a first requested performance corner, receiving, by the processor from a second client powered by the shared power rail, a second requested performance corner, determining by the processor a first peak current value based on the first requested performance corner, determining by the processor a second peak current value based on the second requested performance corner, determining by the processor a system voltage droop margin based on the first peak current value, the second peak current value, and an impedance value of the PDN, and adjusting a voltage of the shared power rail based on the system voltage droop margin.

公开(公告)号：US20240224467A1

公开(公告)日：2024-07-04

申请号：US18147412

申请日：2022-12-28

Applicant: QUALCOMM Incorporated

Inventor： Vijayakumar Ashok DIBBAD ,  Jeffrey GEMAR

IPC: H05K7/20 ,  G06F1/20

CPC classification number: H05K7/20281 ,  G06F1/206

Abstract: Methods for thermal cooling implemented by a processor of a thermal cooling system may include receiving a power profile input associated with a power consuming unit cooled by a coolant within the thermal cooling system, estimating a peak Tj of the power consuming unit during an upcoming interval based on the power profile input, a coolant temperature regulation point, and a coolant flow rate, and changing at least one of the coolant temperature regulation point or the coolant flow rate in response to the estimated peak Tj varying from a predesignated Tj limit by a predetermined threshold.

公开(公告)号：US20230031310A1

公开(公告)日：2023-02-02

申请号：US17390215

申请日：2021-07-30

Applicant: QUALCOMM INCORPORATED

Inventor： ENGIN IPEK ,  Bohuslav RYCHLIK ,  George PATSILARAS ,  Prajakt KULKARNI ,  Can HANKENDI ,  Fahad ALI ,  Jeffrey GEMAR ,  Matthew SEVERSON

IPC: G06F13/16

Abstract: The energy consumed by data transfer in a computing device may be reduced by transferring data that has been encoded in a manner that reduces the number of one “1” data values, the number of signal level transitions, or both. A data destination component of the computing device may receive data encoded in such a manner from a data source component of the computing device over a data communication interconnect, such as an off-chip interconnect. The data may be encoded using minimum Hamming weight encoding, which reduces the number of one “1” data values. The received data may be decoded using minimum Hamming weight decoding. For other computing devices, the data may be encoded using maximum Hamming weight encoding, which increases the number of one “1” data values while reducing the number of zero “0” values, if reducing the number of zero values reduces energy consumption.

公开(公告)号：US20160091939A1

公开(公告)日：2016-03-31

申请号：US14497258

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Matthew Levi SEVERSON ,  Shih-Hsin Jason HU ,  Dipti Ranjan PAL ,  Madan KRISHNAPPA ,  Jeffrey GEMAR ,  Noman AHMED ,  Mohammad TAMJIDI ,  Mark KEMPFERT

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  G06F9/4405 ,  Y02D10/171

Abstract: A method for operating an electronic apparatus is provided. The method includes receiving a token, activating a power switch for powering up a core in response to the receiving the token, and outputting the token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. In one aspect, an electronic apparatus includes a power switch configured to power up to a core is provided. A power-switch control circuit is configured to receive a token, activate the power switch for powering up the core in response to receiving the token, output the received token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. A plurality of the power-switch control circuits is configured as a ring.

Abstract translation: 提供一种操作电子设备的方法。 该方法包括接收令牌，激活用于响应于接收到令牌的核心的电源开关，以及基于为核心加电的状态来输出令牌。 接收的令牌的输出被延迟直到达到核心的加电状态。 在一个方面，一种电子设备包括配置成提供电源至核心的电源开关。 功率开关控制电路被配置为接收令牌，激活电源开关以响应于接收到令牌来加电核心，基于为核心加电的状态输出接收到的令牌。 接收的令牌的输出被延迟直到达到核心的加电状态。 多个电源开关控制电路被配置为环。