公开(公告)号：US09473149B1

公开(公告)日：2016-10-18

申请号：US14991790

申请日：2016-01-08

Applicant: QUALCOMM Incorporated

Inventor： Junmou Zhang ,  Taesik Na ,  Guoan Zhong ,  Nan Chen

IPC: H03L1/02 ,  H03K3/03 ,  G05F3/26

CPC classification number: H03L1/022 ,  G05F3/262 ,  H03K3/011 ,  H03K3/0315 ,  H03L1/02

Abstract: A signal generator configured to generate an oscillating signal with a temperature-compensated frequency. The signal generator includes a ring oscillator, and a complementary to absolute temperature (CTAT) current generator configured to generate a CTAT current for the ring oscillator to temperature-compensate the frequency of the oscillating signal.

Abstract translation: 信号发生器，被配置为产生具有温度补偿频率的振荡信号。 信号发生器包括环形振荡器和与绝对温度（CTAT）电流发生器互补的配置以产生用于环形振荡器的CTAT电流以对振荡信号的频率进行温度补偿。

公开(公告)号：US09281934B2

公开(公告)日：2016-03-08

申请号：US14268850

申请日：2014-05-02

Applicant: QUALCOMM Incorporated

Inventor： Yu Song ,  Jan Christian Diffenderfer ,  Nan Chen ,  David Ian West ,  Paul Lawrence Viani

IPC: H04L7/00 ,  H04L25/00 ,  H04L25/40 ,  H03L7/091 ,  H03L7/08 ,  H04L7/033

CPC classification number: H04L7/0016 ,  H03L7/0807 ,  H03L7/091 ,  H04L7/0083 ,  H04L7/0338

Abstract: Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.

Abstract translation: 公开了用于从数据输入信号恢复时钟和数据的系统和方法，用数据输入信号对多个时钟相位信号进行采样，以确定数据输入信号和时钟相位信号之间的定时关系，并使用确定的定时关系 选择一个时钟相位信号用于采样数据输入信号以产生恢复的数据。 CDR可以包括毛刺抑制模块，以抑制可能由数据输入信号上的大的瞬时抖动引起的时钟输出信号的毛刺。 使用这些方法的时钟和数据恢复电路（CDR）可以快速锁定到新的数据输入信号，并且可以在数据输入信号上存在大的瞬时定时抖动时可靠地接收数据。

公开(公告)号：US20150108842A1

公开(公告)日：2015-04-23

申请号：US14056851

申请日：2013-10-17

Applicant: QUALCOMM Incorporated

Inventor： Nan Chen ,  Narasimhan Vasudevan ,  Michael Thomas Fertsch

IPC: H02J1/00

CPC classification number: H02J1/108 ,  H02J1/10 ,  Y10T307/549

Abstract: Techniques for reducing cross-supply current are described herein. In one embodiment, a power circuit comprises a bypass switch coupled between a first power supply and an internal power supply, and a voltage regulator coupled between a second power supply and the internal power supply. The power circuit also comprises a shut-off circuit configured to detect the first power supply powering up before the second power supply during a power-up sequence, to shut off the bypass switch upon detecting the first power supply powering up before the second power supply, to detect the second power supply powering up during the power-up sequence, and to release control of the bypass switch to a controller upon detecting the second power supply powering up.

Abstract translation: 本文描述了用于降低交叉电源电流的技术。 在一个实施例中，电源电路包括耦合在第一电源和内部电源之间的旁路开关以及耦合在第二电源和内部电源之间的电压调节器。 电源电路还包括关断电路，被配置为在上电序列期间检测在第二电源之前供电的第一电源，以在检测到在第二电源之前检测到第一电源供电时关闭旁路开关 检测在上电序列期间上电的第二电源，并且在检测到第二电源供电时，将旁路开关的控制释放到控制器。

公开(公告)号：US20150106538A1

公开(公告)日：2015-04-16

申请号：US14055761

申请日：2013-10-16

Applicant: QUALCOMM Incorporated

Inventor： Narasimhan Vasudevan ,  Li Pan ,  Michael Thomas Fertsch ,  Nan Chen

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0671 ,  G06F13/1668 ,  G11C7/10 ,  Y02D10/14

Abstract: A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.

Abstract translation: 本文描述了用于存储器读取的接收器架构。 在一个实施例中，存储器接口包括多个发射器，其中多个发射器中的每一个被配置成通过多个I / O通道中的相应一个发射数据到存储器装置。 所述存储器接口还包括多个接收器，其中所述多个接收器中的每一个接收器耦合到所述多个发射器中的相应一个，并且被配置为通过所述多个I / O中的相应一个I / O从所述存储器装置接收数据 频道 多个接收机被分组在一起，位于远离多个发射机的接收机子系统中。

公开(公告)号：US11769740B2

公开(公告)日：2023-09-26

申请号：US17494747

申请日：2021-10-05

Applicant: QUALCOMM Incorporated

Inventor： Alan Lewis ,  Zhengming Fu ,  Nan Chen ,  Adam Polak ,  Laura Fuentes ,  Gregory Bullard ,  Mark Todorovich

IPC: H01L23/00 ,  H01L27/144 ,  G06F21/75

CPC classification number: H01L23/576 ,  G06F21/755 ,  H01L27/1443

Abstract: Various embodiments include integrated approaches to detecting attempts to breach system-level or chip-level security using photo-generated currents induced by lasers or other radiation sources. Various embodiments integrate photo-detection circuits with a secure processor or other circuit in such a manner that the response to a security attack is fast enough to prevent loss of secure or private information are described. Various embodiments include circuits capable of providing a permanent record of photocurrent detection.

公开(公告)号：US20190132137A1

公开(公告)日：2019-05-02

申请号：US15802354

申请日：2017-11-02

Applicant: QUALCOMM Incorporated

Inventor： Guoan Zhong ,  Nan Chen ,  Junmou Zhang

IPC: H04L9/32

Abstract: Aspects of the disclosure are directed to a low noise physically unclonable function (PUF) cell. In accordance with one aspect, the low noise physically unclonable function (PUF) cell includes a first inverter, wherein the first inverter is configured in a negative feedback configuration; and a second inverter coupled to the first inverter in a series configuration, wherein the second inverter is configured in a first open loop configuration.

公开(公告)号：US20180145686A1

公开(公告)日：2018-05-24

申请号：US15358494

申请日：2016-11-22

Applicant: QUALCOMM Incorporated

Inventor： Guoan Zhong ,  Junmou Zhang ,  Nan Chen

IPC: H03K17/687 ,  H03K19/21 ,  H03K3/03 ,  G06F1/32

CPC classification number: H03K17/6871 ,  G01R19/252 ,  G06F1/3206 ,  G06F1/324 ,  H03K19/0016 ,  H03K19/21

Abstract: An apparatus for sensing distributed load currents provided by power gating circuit. The apparatus includes a power gating circuit including a set of bulk transistors coupled in series with a set of circuits between first and second voltage rails. The apparatus includes a current sensor with a first ring oscillator, a first frequency-to-code (FTC) converter, a second ring oscillator, a second FTC converter, and a subtractor. The first ring oscillator includes a first set of one or more inverters configured to receive a first voltage at a node between the power gating circuit and the first circuit, and a second set of one or more inverters configured to receive a second voltage at a second node between the power gating circuit and the second circuit. The first ring oscillator is configured to generate a signal including a frequency related to the voltage drops across the first and second sets of transistors.

公开(公告)号：US09816872B2

公开(公告)日：2017-11-14

申请号：US14300110

申请日：2014-06-09

Applicant: QUALCOMM Incorporated

Inventor： Junmou Zhang ,  Chuang Zhang ,  Nan Chen

IPC: G01K7/01 ,  G01K13/00 ,  G01K15/00

CPC classification number: G01K7/015 ,  G01K13/00 ,  G01K15/005

Abstract: Systems and methods for sensing temperature on a chip are described herein. In one embodiment, a temperature sensor comprises a first transistor having a gate, a second transistor having a gate coupled to the gate of the first transistor, and a bias circuit configured to bias the gates of the first and second transistors such that the first and second transistors operate in a sub-threshold region, and to generate a current proportional to a difference between a gate-to-source voltage of the first transistor and a gate-to-source voltage of the second transistor. The temperature sensor also comprises an analog-to-digital converter (ADC) configured to convert the current into a digital temperature reading.

公开(公告)号：US09640247B2

公开(公告)日：2017-05-02

申请号：US14597146

申请日：2015-01-14

Applicant: QUALCOMM Incorporated

Inventor： Nan Chen ,  Junmou Zhang ,  Min Chen

IPC: G06F7/58 ,  G11C11/417 ,  G11C7/10

CPC classification number: G11C11/417 ,  G06F7/588 ,  G11C7/1006

Abstract: One feature pertains to a true random number generator that utilizes the settling time of a bit cell as an entropy source to generate random digital output values. The bit cell may be a static random access memory bit cell. The bit cell's settling time may be converted into a digital output using an analog to digital converter. A plurality of bit cells may serially couple to one another in a ring formation. The bit cell ring can then be enabled such that each bit cell of the plurality of bit cells achieves a settling value that activates the subsequent bit cell in the ring causing it to in turn reach a settling value, and so on. An output node of one of the bit cells in the ring can then be sampled using a flip-flop to generate a continuous stream of random bits.

公开(公告)号：US20160202953A1

公开(公告)日：2016-07-14

申请号：US14597146

申请日：2015-01-14

Applicant: QUALCOMM Incorporated

Inventor： Nan Chen ,  Junmou Zhang ,  Min Chen

IPC: G06F7/58 ,  G11C11/417

CPC classification number: G11C11/417 ,  G06F7/588 ,  G11C7/1006

Abstract: One feature pertains to a true random number generator that utilizes the settling time of a bit cell as an entropy source to generate random digital output values. The bit cell may be a static random access memory bit cell. The bit cell's settling time may be converted into a digital output using an analog to digital converter. A plurality of bit cells may serially couple to one another in a ring formation. The bit cell ring can then be enabled such that each bit cell of the plurality of bit cells achieves a settling value that activates the subsequent bit cell in the ring causing it to in turn reach a settling value, and so on. An output node of one of the bit cells in the ring can then be sampled using a flip-flop to generate a continuous stream of random bits.

Abstract translation: 一个特征涉及一个真正的随机数发生器，其利用位单元的建立时间作为熵源来产生随机数字输出值。 位单元可以是静态随机存取存储器位单元。 位单元的建立时间可以使用模数转换器转换成数字输出。 多个位单元可以以环形形式彼此串联耦合。 然后可以启用比特单元环，使得多个比特单元中的每个比特单元实现一个建立值，该建立值激活环中随后的比特单元，从而使得其依次达到一个稳定值，依此类推。 然后可以使用触发器对环中的一个比特单元的输出节点进行采样，以生成连续的随机比特流。