公开(公告)号：US20190027435A1

公开(公告)日：2019-01-24

申请号：US16144127

申请日：2018-09-27

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Kambiz Samadi ,  Jing Xie ,  Yang Du

IPC: H01L23/528 ,  H01L25/00 ,  H01L23/522 ,  H01L27/06 ,  H01L23/48 ,  H01L25/065

Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

公开(公告)号：US09508615B2

公开(公告)日：2016-11-29

申请号：US14617901

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Kambiz Samadi ,  Pratyush Kamal ,  Yang Du

IPC: H01L23/58 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L22/20 ,  H01L22/32 ,  H01L23/5256 ,  H01L23/5382 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06596

Abstract: To enable low cost pre-bond testing for a three-dimensional (3D) integrated circuit, a backbone die may have a fully connected two-dimensional (2D) clock tree and one or more non-backbone die may have multiple isolated 2D clock trees. In various embodiments, clock sinks on the backbone die and the non-backbone die can be connected using multiple through-silicon-vias and the isolated 2D clock trees in the non-backbone die can be further connected via a Detachable tree (D-tree), which may comprise a rectilinear minimum spanning tree representing a shortest interconnect among the sinks associated with the 2D clock trees in the non-backbone die. Accordingly, the backbone die and the non-backbone die can be separated and individually tested prior to bonding using one clock probe pad, and the D-tree may be easily removed from the non-backbone die subsequent to the pre-bond testing by burning fuses at the sinks associated with the 2D clock trees.

Abstract translation: 为了实现三维（3D）集成电路的低成本预键测试，主干管芯可以具有完全连接的二维（2D）时钟树，并且一个或多个非主干管芯可以具有多个隔离的2D时钟树 。 在各种实施例中，可以使用多个通硅通孔来连接骨干管芯和非骨干管芯上的时钟汇聚点，并且非骨干管芯中的隔离的2D时钟树可以通过可分离树（D-tree）进一步连接 ），其可以包括表示与非主干管芯中的2D时钟树相关联的汇之间的最短互连的直线最小生成树。 因此，在使用一个时钟探针焊盘进行粘合之前，主骨架和非主干裸片可以被分离和单独测试，并且在通过燃烧进行预键合测试之前，D树可以容易地从非主干模具移除 在与2D时钟树相关联的接收器处保险丝。

公开(公告)号：US20150121327A1

公开(公告)日：2015-04-30

申请号：US14159028

申请日：2014-01-20

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du

IPC: G06F17/50

CPC classification number: G06F1/10 ,  G06F17/5031 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/62 ,  G06F2217/84 ,  H01L27/0688

Abstract: Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems are disclosed. Methods and related components are also disclosed. In an exemplary embodiment, to offset the skew that may result across the tiers in the clock tree, a cross-tier clock balancing scheme makes use of automatic delay adjustment. In particular, a delay sensing circuit detects a difference in delay at comparable points in the clock tree between different tiers and instructs a programmable delay element to delay the clock signals on the faster of the two tiers. In a second exemplary embodiment, a metal mesh is provided to all elements within the clock tree and acts as a signal aggregator that provides clock signals to the clocked elements substantially simultaneously.

Abstract translation: 公开了单片三维（3D）集成电路（IC）（3DIC）跨层时钟偏移管理系统。 还公开了方法和相关组件。 在示例性实施例中，为了抵消可能在时钟树中的层次之间产生的偏斜，跨层时钟平衡方案​​利用自动延迟调整。 特别地，延迟感测电路检测不同层之间的时钟树中可比较点的延迟差异，并且指示可编程延迟元件在两个层级中更快地延迟时钟信号。 在第二示例性实施例中，金属网格被提供给时钟树中的所有元件，并且用作基本上同时向时钟元件提供时钟信号的信号聚合器。

公开(公告)号：US09537471B2

公开(公告)日：2017-01-03

申请号：US14617885

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal

IPC: H03K3/356 ,  H03K3/012 ,  H03K3/3562 ,  G11C19/28 ,  H01L27/06 ,  G11C19/34

CPC classification number: H03K3/356182 ,  G11C19/28 ,  G11C19/34 ,  H01L27/0688 ,  H03K3/012 ,  H03K3/35606 ,  H03K3/35625

Abstract: A 3D multi-bit flip-flop may include a two tier structure. The two tier structure may include a first tier containing a common clock circuit for the multi-bit flip-flop as well as the clock driven portions of the individual flip-flops and a second tier containing a common scan circuit for the multi-bit flip-flop as well as the non-clock driven portions of the individual flip-flops. Alternatively, the first tier may include the common clock circuit as well as a portion of the individual flip-flops and the second tier may include the common scan circuit as well as the other portion of the individual flip-flops.

Abstract translation: 3D多位触发器可以包括两层结构。 双层结构可以包括第一层，其包含用于多位触发器的公共时钟电路以及各个触发器的时钟驱动部分，以及包含用于多位触发器的公共扫描电路的第二层 -flop以及各个触发器的非时钟驱动部分。 或者，第一层可以包括公共时钟电路以及单个触发器的一部分，并且第二层可以包括公共扫描电路以及各个触发器的另一部分。

公开(公告)号：US09093995B2

公开(公告)日：2015-07-28

申请号：US13905052

申请日：2013-05-29

Applicant: QUALCOMM Incorporated

Inventor： Kashyap Ramachandra Bellur ,  HariKrishna Chintarlapalli Reddy ,  Martin Saint-Laurent ,  Pratyush Kamal ,  Prayag Bhanubhai Patel ,  Esin Terzioglu

IPC: H03K3/012 ,  H03K3/037 ,  G06F17/50 ,  H03K3/356

CPC classification number: H03K3/037 ,  G06F17/5068 ,  G06F17/5081 ,  H03K3/012 ,  H03K3/356

Abstract: A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.

Abstract translation: 电路包括脉冲锁存电路。 脉冲锁存电路包括第一多个晶体管。 第一多个晶体管中的一个或多个是扩散长度（LOD）保护的。

公开(公告)号：US20150022250A1

公开(公告)日：2015-01-22

申请号：US14012445

申请日：2013-08-28

Applicant: Qualcomm Incorporated

Inventor： Pratyush Kamal ,  Yang Du

IPC: H03K3/037 ,  G06F17/50

CPC classification number: H03K3/0372 ,  G06F17/5068 ,  H01L27/0688 ,  H03K3/35625

Abstract: Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods are disclosed. The present disclosure provides a 3D integrated circuit (IC) (3DIC) that has a flop spread across at least two tiers of the 3DIC. The flop is split across tiers with transistor partitioning in such a way that keeps all the clock related devices at the same tier, thus potentially giving better setup, hold and clock-to-q margin. In particular, a first tier of the 3DIC has the master latch, slave latch, and clock circuit. A second tier has the input circuit and the output circuit.

Abstract translation: 公开了具有最小时钟偏移和相关系统和方法的单片三维（3D）触发器。 本公开提供了具有翻转的3D集成电路（3DIC）（3DIC），其跨越3DIC的至少两层。 触发器分为跨级别，晶体管分区，使得所有与时钟相关的器件保持在同一层级，从而可能提供更好的设置，保持和时钟到余裕。 特别地，3DIC的第一层具有主锁存器，从锁存器和时钟电路。 第二层有输入电路和输出电路。

公开(公告)号：US20140354338A1

公开(公告)日：2014-12-04

申请号：US13905052

申请日：2013-05-29

Applicant: QUALCOMM Incorporated

Inventor： Kashyap Ramachandra Bellur ,  HariKrishna Chintarlapalli Reddy ,  Martin Saint-Laurent ,  Pratyush Kamal ,  Prayag Bhanubhai Patel ,  Esin Terzioglu

IPC: H03K3/037 ,  G06F17/50

CPC classification number: H03K3/037 ,  G06F17/5068 ,  G06F17/5081 ,  H03K3/012 ,  H03K3/356

Abstract: A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.

Abstract translation: 电路包括脉冲锁存电路。 脉冲锁存电路包括第一多个晶体管。 第一多个晶体管中的一个或多个是扩散长度（LOD）保护的。

公开(公告)号：US20180286800A1

公开(公告)日：2018-10-04

申请号：US15472614

申请日：2017-03-29

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Kambiz Samadi ,  Jing Xie ,  Yang Du

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/522 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/528 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5286 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544

Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

公开(公告)号：US20150325563A1

公开(公告)日：2015-11-12

申请号：US14272981

申请日：2014-05-08

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du

IPC: H01L27/02 ,  H01L27/12 ,  H03K3/012 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/78696 ,  H03K3/012

Abstract: Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having gate back-bias rail(s) are disclosed. Related systems and methods are also disclosed. In one aspect, a SOI CMOS standard library cell circuit is provided that is comprised of one or more standard library cells. Each standard library cell includes one or more PMOS channel regions and one or more NMOS channel regions. Each standard library cell has one or more gate back-bias rails disposed adjacent to PMOS and NMOS channel regions. The gate back-bias rails are configured to apply bias voltages to corresponding PMOS and NMOS channel regions to adjust threshold voltages of PMOS and NMOS transistors associated with the PMOS and NMOS channel regions, respectively. Voltage biasing can be controlled to adjust timing of an IC using SOI CMOS standard library cell circuits to achieve design timing targets without including timing closure elements that consume additional area.

Abstract translation: 公开了具有栅极背偏置导轨的绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）标准库单元电路。 还公开了相关系统和方法。 在一个方面，提供了由一个或多个标准库单元组成的SOI CMOS标准库单元电路。 每个标准库单元包括一个或多个PMOS沟道区和一个或多个NMOS沟道区。 每个标准库单元具有邻近PMOS和NMOS沟道区设置的一个或多个栅极偏置导轨。 栅极反向偏置导轨被配置为向相应的PMOS和NMOS沟道区域施加偏置电压，以分别调整与PMOS和NMOS沟道区相关联的PMOS和NMOS晶体管的阈值电压。 可以控制电压偏置，以调整使用SOI CMOS标准库单元电路的IC的定时，以实现设计时序目标，而不包括消耗额外面积的时序闭合元件。

公开(公告)号：US09147438B2

公开(公告)日：2015-09-29

申请号：US14152248

申请日：2014-01-10

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du ,  Kambiz Samadi

IPC: G11C17/00 ,  G11C5/02 ,  H04L12/933 ,  H01L23/00 ,  G06F1/32 ,  H01L27/06

CPC classification number: G11C5/02 ,  G06F1/3225 ,  G06F1/3275 ,  G11C5/025 ,  G11C5/063 ,  H01L24/89 ,  H01L27/0688 ,  H01L2924/1434 ,  H04L49/101 ,  H04L49/109 ,  Y02D10/13 ,  Y02D10/14

Abstract: Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components are disclosed. A 3D memory crossbar architecture with tight-pitched vertical monolithic intertier vias (MIVs) for inter-block routing and multiplexers at each tier for block access is used to shorten overall conductor length and reduce resistive-capacitive (RC) delay. Elimination of such long crossbars reduces the RC delay of the crossbar and generally improves performance and speed. Further, elimination of the long horizontal crossbars makes conductor routing easier. The MIVs, with their small run-length, can work without the need for repeaters (unlike the long crossbars), and control logic may be used to configure the memory banks based on use.

Abstract translation: 公开了具有垂直存储器组件的单片三维（3D）集成电路（IC）（3DIC）。 使用具有用于块间路由选择的紧密垂直单片中间层通道（MIV）的三维存储器交叉结构架构，用于块访问的每层级多路复用器，以缩短整体导体长度并降低电阻 - 电容（RC）延迟。 消除这种长的十字准线会降低交叉开关的RC延迟，并通常提高性能和速度。 此外，消除长的横向横梁使得导线布线更容易。 MIVs具有较小的长度，可以在不需要中继器的情况下工作（与长十字准线不同），并且可以使用控制逻辑来基于使用配置存储体。