公开(公告)号：US09933827B2

公开(公告)日：2018-04-03

申请号：US13771064

申请日：2013-02-19

Applicant: QUALCOMM Incorporated

Inventor： Ajay Cheriyan ,  Rajesh Joshi ,  Madan Krishnappa

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3296 ,  Y02D10/172 ,  Y10T307/406

Abstract: Various aspects of a power management approach for a system-on-a-chip (SoC) is disclosed herein. In one aspect, the approach includes implementing a power profile for supplying power to a plurality of subsystems on a shared power bus in the SoC. The power profile includes at least one adjustable parameter for controlling the supplied power during an active use state. The approach further includes detecting a power profile change trigger; modifying the power profile based on the power profile change trigger; and adjusting the supplied power during the active use state based on the modified power profile to maintain a predetermined supplied power level.

公开(公告)号：US20140232188A1

公开(公告)日：2014-08-21

申请号：US13771064

申请日：2013-02-19

Applicant: QUALCOMM INCORPORATED

Inventor： Ajay Cheriyan ,  Rajesh Joshi ,  Madan Krishnappa

IPC: H02J1/00

CPC classification number: G06F1/3206 ,  G06F1/3296 ,  Y02D10/172 ,  Y10T307/406

Abstract: Various aspects of a power management approach for a system-on-a-chip (SoC) is disclosed herein. In one aspect, the approach includes implementing a power profile for supplying power to a plurality of subsystems on a shared power bus in the SoC. The power profile includes at least one adjustable parameter for controlling the supplied power during an active use state. The approach further includes detecting a power profile change trigger; modifying the power profile based on the power profile change trigger; and adjusting the supplied power during the active use state based on the modified power profile to maintain a predetermined supplied power level

Abstract translation: 本文公开了片上系统（SoC）的功率管理方法的各个方面。 在一个方面，该方法包括实现用于向SoC中的共享电力总线上的多个子系统供电的功率分布。 功率分布包括用于在主动使用状态期间控制供电的至少一个可调参数。 该方法还包括检测功率分布变化触发; 基于功率分布变化触发来修改功率曲线; 以及基于所述修改的功率曲线在所述主动使用状态期间调整所提供的功率以维持预定的供电功率水平

公开(公告)号：US12135678B2

公开(公告)日：2024-11-05

申请号：US18041168

申请日：2021-04-23

Applicant: QUALCOMM INCORPORATED

Inventor： Uttkarsh Wardhan ,  Vishal Ghorpade ,  Sanku Mukherjee ,  Madan Krishnappa ,  Sanath Sreekanta ,  Pankhuri Agarwal ,  Santanu Pattanayak

IPC: G06F15/78 ,  G05B13/00

Abstract: The reliability of a data communication link may be analyzed and otherwise maintained by collecting a two-dimensional array representing a functional data eye, and using a convolutional neural network to determine a score of the functional data eye. The determined score may be compared with a threshold, and an action may be initiated based on the result of the comparison.

公开(公告)号：US20140157007A1

公开(公告)日：2014-06-05

申请号：US13692735

申请日：2012-12-03

Applicant: QUALCOMM INCORPORATED

Inventor： Madan Krishnappa

IPC: H02J4/00 ,  G06F1/28

CPC classification number: H02J4/00 ,  G06F1/28 ,  G06F1/3296 ,  Y02D10/172

Abstract: A particular method includes, prior to issuing a recommendation by an adaptive voltage scaling (AVS) system, performing a first iteration of an AVS operation to sample characteristics of a semiconductor device to determine a first adjustment recommendation. The method further includes performing at least one additional iteration of the AVS operation to determine at least one additional adjustment iteration. When a threshold number of consecutive adjustment recommendations are consistent, the method includes issuing the recommendation by the AVS system.

Abstract translation: 一种特定的方法包括，在通过自适应电压缩放（AVS）系统发布推荐之前，执行AVS操作的第一次迭代来采样半导体器件的特性以确定第一调整推荐。 该方法还包括执行AVS操作的至少一次附加迭代以确定至少一个附加的调整迭代。 当连续调整建议的阈值数量一致时，该方法包括由AVS系统发布推荐。

公开(公告)号：US11934219B2

公开(公告)日：2024-03-19

申请号：US17707621

申请日：2022-03-29

Applicant: QUALCOMM Incorporated

Inventor： Arvind Jain ,  Divya Gangadharan ,  Muhammad Nasir ,  Hong Dai ,  Madan Krishnappa

IPC: G06F1/06 ,  G01R31/317 ,  H04B1/401

CPC classification number: G06F1/06 ,  G01R31/31727 ,  H04B1/401

Abstract: An aspect of the disclosure relates to an integrated circuit (IC). The IC includes a first set of test clock controllers (TCCs) including a first set of clock outputs, respectively; and a first set of functional cores including a first set of clock inputs coupled to the first set of clock outputs of the first set of TCCs, respectively.

公开(公告)号：US10114443B2

公开(公告)日：2018-10-30

申请号：US15441124

申请日：2017-02-23

Applicant: QUALCOMM Incorporated

Inventor： Rajat Mittal ,  Madan Krishnappa ,  Rajit Chandra ,  Mohammad Tamjidi

IPC: G06F1/32 ,  G06F1/20 ,  G06F9/50 ,  G06F9/48

Abstract: A thermal controller for managing thermal energy of a multi-core processor is provided. The cores include a first core processing a load and remaining cores. The thermal controller is configured to determine that a temperature of the first core is greater than a first threshold, determine a temperature of a second core of the remaining cores in response to determining that the temperature of the first core is greater than the first threshold, and determine whether the temperature of the second core is greater than or less than a second threshold. The thermal controller is configured to transfer at least a portion of the load of the first core to the second core in response to determining that the temperature of the first core is greater than the first threshold and based on whether the temperature of the second core is greater than or less than the second threshold.

公开(公告)号：US20140191794A1

公开(公告)日：2014-07-10

申请号：US13736295

申请日：2013-01-08

Applicant: QUALCOMM INCORPORATED

Inventor： Madan Krishnappa ,  Stephen Simmonds ,  Parag Arun Agashe ,  Sajjad Pagarkar ,  Ashwin Rabindranath ,  Sagar Digwalekar

IPC: G05F1/10

CPC classification number: G05F1/10 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/172 ,  Y02D50/20

Abstract: An integrated circuit (IC) includes an adaptive voltage scaling (AVS) controller configured to control a voltage supplied to a portion of the IC and at least one sensor configured to sense at least one state of the IC and to provide an output signal indicative of the at least one sensed state to the AVS controller, the IC having a first setting and a second setting, the AVS controller being configured to use the output signal to control the voltage in the first setting and the AVS controller being configured to control the voltage independently of the output signal in the second setting. Also a method of performing AVS is provided.

Abstract translation: 集成电路（IC）包括自适应电压调节（AVS）控制器，其被配置为控制提供给IC的一部分的电压以及被配置为感测IC的至少一个状态的至少一个传感器，并且提供指示 所述至少一个感测状态到所述AVS控制器，所述IC具有第一设置和第二设置，所述AVS控制器被配置为使用所述输出信号来控制所述第一设置中的电压，并且所述AVS控制器被配置为控制所述电压 独立于第二设置中的输出信号。 还提供了一种执行AVS的方法。

公开(公告)号：US11250197B1

公开(公告)日：2022-02-15

申请号：US17079727

申请日：2020-10-26

Applicant: QUALCOMM Incorporated

Inventor： Vinod Kumar Lakshmipathi ,  Venugopal Sanaka ,  Babu Suriamoorthy ,  Madan Krishnappa ,  Pavan Kumar Patibanda

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/347 ,  G06F30/394 ,  G06F115/06 ,  G06F115/10 ,  G06F115/02 ,  G06F119/06

Abstract: Various embodiments may include integrated circuits (ICs) and methods for designing an integrated circuit (IC), such as a system-on-chip (SOC). Embodiments include methods for planning and producing ICs without communication channels, also referred to as channel-less ICs. Embodiments may include overlay hard macros that support routing and communication design without dedicated communication channels being needed between functional hard macros, such as cores of a SOC. Various embodiments may include an IC in which one or more interconnect hard macros and wires connecting a first functional hard macro, a second functional hard macro and the one or more interconnect hard macros are located within a third functional hard macro. In some embodiments, no communication channel may be present between the first functional hard macro, the second functional hard macro, and the third functional hard macro.

公开(公告)号：US09846612B2

公开(公告)日：2017-12-19

申请号：US14823879

申请日：2015-08-11

Applicant: QUALCOMM INCORPORATED

Inventor： Madan Krishnappa ,  Chinh Tran ,  Li Zhang ,  Alan Young ,  William Bainbridge ,  Bohuslav Rychlik

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11 ,  G06F1/32 ,  G06F11/30 ,  G11B20/18

CPC classification number: G06F11/10 ,  G06F1/3206 ,  G06F1/3296 ,  G06F11/1008 ,  G06F11/1048 ,  G06F11/3058 ,  G06F11/3062 ,  G11B20/1816 ,  H03M13/11 ,  H03M13/611 ,  H03M13/6505 ,  Y02D10/172

Abstract: Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.

公开(公告)号：US09612636B2

公开(公告)日：2017-04-04

申请号：US14497258

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Matthew Levi Severson ,  Shih-Hsin Jason Hu ,  Dipti Ranjan Pal ,  Madan Krishnappa ,  Jeffrey Gemar ,  Noman Ahmed ,  Mohammad Tamjidi ,  Mark Kempfert

IPC: G06F1/32 ,  G06F1/26 ,  G06F9/44

CPC classification number: G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  G06F9/4405 ,  Y02D10/171

Abstract: A method for operating an electronic apparatus is provided. The method includes receiving a token, activating a power switch for powering up a core in response to the receiving the token, and outputting the token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. In one aspect, an electronic apparatus includes a power switch configured to power up to a core is provided. A power-switch control circuit is configured to receive a token, activate the power switch for powering up the core in response to receiving the token, output the received token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. A plurality of the power-switch control circuits is configured as a ring.