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公开(公告)号：US20240281401A1
公开(公告)日：2024-08-22
申请号：US18171264
申请日：2023-02-17
发明人： Lalan Jee MISHRA , Richard Dominic WIETFELDT , Umesh SRIKANTIAH , Francesco GATTA , Christopher Kong Yee CHUN
CPC分类号： G06F13/4282 , G06F13/4022 , G06F2213/0018
摘要： A subordinate device participates in address assignment through iterative communication with a host device. The subordinate device receives a first broadcast command over a multidrop serial bus, decouples a daisy chain input of the subordinate device from a daisy chain output of the subordinate device, receives a second broadcast command over the multidrop serial bus, responds to the second broadcast command when a signal received through the daisy chain input is in an active state, ignores the second broadcast command when the signal received through the daisy chain input is in an inactive state, and ignores subsequent broadcast commands after responding to the second broadcast command. Responding to the second broadcast command includes configuring a unique device identifier of the subordinate device using an address provided in the second broadcast command, and coupling the daisy chain input of the subordinate device to the daisy chain output of the subordinate device.
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公开(公告)号：US20200344094A1
公开(公告)日：2020-10-29
申请号：US16392235
申请日：2019-04-23
摘要： Systems, methods, and apparatus for one wire communication are disclosed. An apparatus has a line driver adapted to power one or more slave devices coupled to a one-wire serial bus, a circuit for encoding and decoding data in signals transmitted over the serial bus, and a controller. The line driver may maintain the wire at or above a voltage base level during transactions conducted over the wire. A data-encoded signal provided by the coding circuit may be transmitted on the wire in a first transaction and a data-encoded signal received from the wire may be decoded during a second transaction. The line driver may power the one or more slave devices when it maintains the wire at or above the first voltage level. The first signal and the second signal transitions within a voltage range defined by the first voltage level and a second voltage level.
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3.发明申请公开(公告)号：US20200050575A1
公开(公告)日：2020-02-13
申请号：US16509957
申请日：2019-07-12
IPC分类号： G06F13/42
摘要： Increased data rates over a serial bus are enabled without increasing clock frequency. A method performed at a device coupled to a serial datalink includes transmitting a one-bit sequence start condition over a data wire of a datalink, providing a command field in the pulse-width modulated datagram, where a first-transmitted bit of the command field identifies the datagram as a write command directed to a register located at address zero, and providing data in a third-transmitted bit and subsequently-transmitted bits of the command field to be written to the register located at address zero when a second-transmitted bit of the command field has a first value. The sequence start condition has a first edge that commences transmission of a pulse-width modulated datagram and a second edge that indicates an optimal sampling point in each bit period of the pulse-width modulated datagram.
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公开(公告)号：US20190354505A1
公开(公告)日：2019-11-21
申请号：US16381189
申请日：2019-04-11
IPC分类号： G06F13/42
摘要： Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes providing a data payload for a first data frame to be transmitted over a plurality of data lanes of a multilane serial bus operated in accordance with an I3C protocol, providing one or more indicators of validity of one or more bytes included in the data payload, and transmitting the first data frame over the multilane serial bus in accordance with a clock signal transmitted on a clock lane of the multilane serial bus.
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公开(公告)号：US20190286587A1
公开(公告)日：2019-09-19
申请号：US16262267
申请日：2019-01-30
发明人： Lalan Jee MISHRA , Richard Dominic WIETFELDT , Helena Deirdre O'SHEA , Wolfgang ROETHIG , Christopher Kong Yee CHUN , ZhenQi CHEN , Scott DAVENPORT , Chiew-Guan TAN , Wilson CHEN , Umesh SRIKANTIAH
摘要： Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.
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6.发明申请公开(公告)号：US20190173662A1
公开(公告)日：2019-06-06
申请号：US16173949
申请日：2018-10-29
IPC分类号： H04L7/033
CPC分类号： H04L7/033 , G06F13/4295
摘要： Systems, methods, and apparatus for line multiplexed serial interfaces are disclosed. A method performed by a receiving device includes detecting a first transition in a signal received from a receive line of a UART after the receive line has been idle or following transmission of a stop bit on the receive line, detecting a second transition in the signal, synchronizing a sampling clock to the second transition, where clock cycles of the sampling clock are double the duration between the first transition and the second transition, and using the sampling clock to capture a byte of data from the receive line. One clock cycle of the sampling clock may be consumed while receiving each bit of data.
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公开(公告)号：US20190171590A1
公开(公告)日：2019-06-06
申请号：US16162583
申请日：2018-10-17
IPC分类号： G06F13/16 , G06F3/06 , H04L12/40 , H04L25/497 , H04B7/26
摘要： Systems, methods, and apparatus for optimizing bus latency associated with a serial bus using staggered bidirectional transmission within a transaction or datagram are described. A method performed at a device coupled to a serial bus includes initiating a transaction between the first device and a second device to exchange a datagram with the second device in a first direction over the serial bus, and exchanging one or more bytes of data with the second device in a second direction over the serial bus before the datagram has been completely transmitted. The first device and the second device alternate as transmitters on the serial bus such that direction of data transmission is staggered on the serial bus. The serial bus may be operated in accordance with an I3C, RFFE, SPMI, or other protocol.
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8.发明申请公开(公告)号：US20190171588A1
公开(公告)日：2019-06-06
申请号：US16162508
申请日：2018-10-17
摘要： Systems, methods, and apparatus adapted to transmit coexistence management interface (CxMi) messages over a multi-point serial bus are described. A method performed at a device coupled to a multi-point serial bus includes encoding CxMi state as one or more virtual general-purpose input/output (VGI) messages, and transmitting the VGI messages over the multi-point serial bus in a command code field of a datagram addressed to one or more devices coupled to the multi-point serial bus. The serial bus may be operated in accordance with an RFFE protocol SPMI protocol.
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公开(公告)号：US20180357199A1
公开(公告)日：2018-12-13
申请号：US15994675
申请日：2018-05-31
CPC分类号： G06F13/4282 , G06F13/24 , G06F13/4004 , G06F2213/0016
摘要： Systems, methods, and apparatus for a slave-to-slave communication over a serial communication link are provided. An apparatus includes an interface adapted to couple the apparatus to a serial bus, and a processing circuit. The processing circuit may be configured to receive a request for a slave-to-slave transaction while servicing an in-band interrupt detected on a serial bus, the request for the slave-to-slave transaction indicating a source address and a target address, generate a first frame that includes the source address, the target address and a command code configured to initiate the slave-to-slave transaction between the source slave device and at least one target slave device, and initiate a data transfer on the serial bus between the source slave device and the at least one target slave device by transmitting the first frame on the serial bus.
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公开(公告)号：US20180357194A1
公开(公告)日：2018-12-13
申请号：US15994754
申请日：2018-05-31
IPC分类号： G06F13/362 , G06F13/42
CPC分类号： G06F13/3625 , G06F13/4291
摘要： Systems, methods, and apparatus for optimizing bus turnaround in a master-driven serial bus are described. A method performed at a master device coupled to a serial bus includes configuring slave devices coupled to the serial bus with respective delay values that define bus turnaround wait periods, transmitting a first read command directed to a first slave device, receiving data after a first wait period initiated after the first read command has been sent, the first wait period being defined by a delay value configured in the first slave device, transmitting a second read command directed to a second slave device, and receiving data after a second wait period initiated after the second read command has been sent, the second wait period being defined by a delay value configured in the second slave device. The first wait period and the second wait period may have different durations.
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