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    Intelligent bit line precharge for improved dynamic power
    1.
    发明授权
    Intelligent bit line precharge for improved dynamic power 有权
    智能位线预充电可提高动态功耗

    公开(公告)号：US09514805B1

    公开(公告)日：2016-12-06

    申请号：US15083055

    申请日：2016-03-28

    Applicant: QUALCOMM Incorporated

    Inventor： Arun Babu Pallerla ,  Ritu Chaba

    IPC: G11C11/00 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/1009 ,  G11C7/12

    Abstract: A method and apparatus for writing data to a memory device are provided that do not change the precharge states for a bit line pair in a current write cycle if the current data bit is unchanged from the preceding write cycle.

    Abstract translation: 提供了一种用于将数据写入存储器件的方法和装置，如果当前数据位与前一写周期不变，则不改变当前写周期中的位线对的预充电状态。

    Memory with multiple word line design
    5.
    发明授权
    Memory with multiple word line design 有权
    具有多个字线设计的内存

    公开(公告)号：US08929153B1

    公开(公告)日：2015-01-06

    申请号：US13975254

    申请日：2013-08-23

    Applicant: QUALCOMM Incorporated

    Inventor： Chirag Gulati ,  Rakesh Kumar Sinha ,  Ritu Chaba ,  Sei Seung Yoon

    IPC: G11C7/00 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

    Abstract: Disclosed are various apparatuses and methods for a memory with a multiple read word line design. A memory may include a plurality of bit cells arranged in a row, a first read word line connected to a first subset of the plurality of bit cells, and a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells. A method may include asserting, during a first read operation, a first read word line connected to a first subset of a plurality of bit cells arranged in a row of bit cells, and asserting, during a second read operation, a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells.

    Abstract translation: 公开了具有多重读取字线设计的存储器的各种装置和方法。 存储器可以包括排列成行的多个比特单元，连接到多个比特单元的第一子集的第一读取字线和连接到多个比特单元的第二子集的第二读取字线，其中 第一和第二子集位于同一行位单元格中。 一种方法可以包括在第一读取操作期间断言连接到排列在位单元行中的多个位单元的第一子集的第一读取字线，并且在第二读取操作期间断言第二读取字线 连接到所述多个位单元的第二子集，其中所述第一和第二子集位于同一行比特单元中。

    WEAK KEEPER CIRCUIT FOR MEMORY DEVICE
    6.
    发明申请
    WEAK KEEPER CIRCUIT FOR MEMORY DEVICE 有权
    用于存储器件的弱保护电路

    公开(公告)号：US20140226418A1

    公开(公告)日：2014-08-14

    申请号：US13765533

    申请日：2013-02-12

    Applicant: QUALCOMM INCORPORATED

    Inventor： Balachander Ganesan ,  Ritu Chaba ,  Sei Seung Yoon

    IPC: G11C7/00

    CPC classification number: G11C7/065 ,  G11C7/12 ,  G11C7/18

    Abstract: A memory circuit is provided comprising a plurality of bit cells coupled to a bit line that permits accessing information from each of the plurality of bit cells. A sense inverter is coupled to an output of the bit line. A keeper circuit has an output coupled to the bit line to compensate for current leakage from the plurality of bit cells. The keeper circuit may comprise an n-channel metal-oxide-silicon (NMOS) transistor in series with a p- channel metal-oxide-silicon (PMOS) transistor.

    Abstract translation: 提供一种存储器电路，其包括耦合到位线的多个位单元，其允许访问来自多个位单元中的每一个的信息。 感测反相器耦合到位线的输出端。 保持器电路具有耦合到位线的输出以补偿来自多个位单元的电流泄漏。 保持器电路可以包括与p沟道金属氧化物 - 硅（PMOS）晶体管串联的n沟道金属氧化物 - 硅（NMOS）晶体管。

    Reconfigurable memory interface circuit to support a built-in memory scan chain
    10.
    发明授权
    Reconfigurable memory interface circuit to support a built-in memory scan chain 有权
    可重构存储器接口电路，支持内置的内存扫描链

    公开(公告)号：US09188642B2

    公开(公告)日：2015-11-17

    申请号：US13975277

    申请日：2013-08-23

    Applicant: QUALCOMM Incorporated

    Inventor： Chirag Gulati ,  Ritu Chaba ,  Lakshmikantha Holla Vakwadi

    IPC: G01R31/3185 ,  G11C29/32 ,  G11C29/36

    CPC classification number: G01R31/318541 ,  G01R31/318597 ,  G11C29/32 ,  G11C29/36 ,  G11C2029/3202 ,  G11C2029/3602

    Abstract: A method of operating an apparatus in a functional mode and an ATPG scan mode and an apparatus for use in a functional mode and an ATPG scan mode are provided. The apparatus includes a set of latches including a first latch and a second latch. The first latch is operated as a master latch and the second latch is operated as a master latch in the functional mode. The first latch is operated as a master latch of a flip-flop and the second latch is operated as a slave latch of the flip-flop in the ATPG scan mode. In one configuration, the apparatus includes a plurality of latches including at least the first and second latches, an output of each of the latches is coupled to a digital circuit, the apparatus includes a plurality of functional inputs, and each of the functional inputs is input to the digital circuit.

    Abstract translation: 提供了在功能模式和ATPG扫描模式下操作装置的方法以及用于功能模式和ATPG扫描模式的装置。 该装置包括一组锁存器，其包括第一锁存器和第二锁存器。 第一个锁存器作为主锁存器操作，第二个锁存器在功能模式下作为主锁存器运行。 第一个锁存器作为触发器的主锁存器操作，第二个锁存器在ATPG扫描模式下作为触发器的从锁存器操作。 在一种配置中，该装置包括至少包括第一和第二锁存器的多个锁存器，每个锁存器的输出耦合到数字电路，该装置包括多个功能输入，并且每个功能输入是 输入到数字电路。

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