公开(公告)号：US20210098048A1

公开(公告)日：2021-04-01

申请号：US17018248

申请日：2020-09-11

Applicant: Rambus Inc.

Inventor： Craig E. HAMPEL ,  Richard E. PEREGO ,  Stefanos SIDIROPOULOS ,  Ely K. TSERN ,  Frederick A. WARE

IPC: G11C11/4076 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4078 ,  H04L7/00 ,  G06F12/02 ,  G11C11/406 ,  G11C21/00 ,  G06F3/06 ,  G11C11/4072 ,  G11C11/4093

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

公开(公告)号：US20190214074A1

公开(公告)日：2019-07-11

申请号：US16215275

申请日：2018-12-10

Applicant: Rambus Inc.

Inventor： Craig E. HAMPEL ,  Richard E. PEREGO ,  Stefanos SIDIROPOULOS ,  Ely K. TSERN ,  Frederick A. WARE

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C7/10 ,  G06F3/06 ,  G06F12/02 ,  G11C21/00 ,  G11C11/406 ,  H04L7/00 ,  G11C11/4072 ,  G11C11/4078 ,  G11C7/22

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

公开(公告)号：US20180053544A1

公开(公告)日：2018-02-22

申请号：US15552569

申请日：2016-02-22

Applicant: RAMBUS INC.

Inventor： Frederick A. WARE ,  Ely K. TSERN ,  John Eric LINDSTADT ,  Thomas J. GIOVANNINI ,  Scott C. BEST ,  Kenneth L. WRIGHT

IPC: G11C11/4093 ,  H01L25/18 ,  G11C11/4096 ,  G11C11/4076 ,  H01L25/065 ,  G11C11/408

CPC classification number: G11C11/4093 ,  G11C5/025 ,  G11C5/063 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/824 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/45099

Abstract: A memory system includes dynamic random-access memory (DRAM) component that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.