公开(公告)号：US20230305915A1

公开(公告)日：2023-09-28

申请号：US18092556

申请日：2023-01-03

Applicant: Rambus Inc.

Inventor： Thomas J. GIOVANNINI ,  Catherine CHEN ,  Scott C. BEST ,  John Eric LINSTADT ,  Frederick A. WARE

IPC: G06F11/07 ,  G11C29/44 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0772 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26 ,  G11C29/44

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

公开(公告)号：US20180053544A1

公开(公告)日：2018-02-22

申请号：US15552569

申请日：2016-02-22

Applicant: RAMBUS INC.

Inventor： Frederick A. WARE ,  Ely K. TSERN ,  John Eric LINDSTADT ,  Thomas J. GIOVANNINI ,  Scott C. BEST ,  Kenneth L. WRIGHT

IPC: G11C11/4093 ,  H01L25/18 ,  G11C11/4096 ,  G11C11/4076 ,  H01L25/065 ,  G11C11/408

CPC classification number: G11C11/4093 ,  G11C5/025 ,  G11C5/063 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/824 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/45099

Abstract: A memory system includes dynamic random-access memory (DRAM) component that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

公开(公告)号：US20240320080A1

公开(公告)日：2024-09-26

申请号：US18586907

申请日：2024-02-26

Applicant: Rambus Inc.

Inventor： Thomas J. GIOVANNINI ,  Catherine CHEN ,  Scott C. BEST ,  John Eric LINSTADT ,  Frederick A. WARE

IPC: G06F11/07 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26 ,  G11C29/44

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0772 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26 ,  G11C29/44

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

公开(公告)号：US20210303383A1

公开(公告)日：2021-09-30

申请号：US17236445

申请日：2021-04-21

Applicant: Rambus Inc.

Inventor： Thomas J. GIOVANNINI ,  Catherine CHEN ,  Scott C. BEST ,  John Eric LINSTADT ,  Frederick A. WARE

IPC: G06F11/07 ,  G11C29/44 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

公开(公告)号：US20190179690A1

公开(公告)日：2019-06-13

申请号：US16183470

申请日：2018-11-07

Applicant: Rambus Inc.

Inventor： Thomas J. GIOVANNINI ,  Catherine CHEN ,  Scott C. BEST ,  John Eric LINSTADT ,  Frederick A. WARE

IPC: G06F11/07 ,  G11C29/26 ,  G11C8/12 ,  G11C7/20 ,  G11C29/44 ,  G06F13/00 ,  G11C5/04

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.