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公开(公告)号：US20250069644A1
公开(公告)日：2025-02-27
申请号：US18882372
申请日：2024-09-11
Applicant: Rambus Inc.
Inventor： Jared L. ZERBE , Frederick A. WARE
Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.
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2.发明公开公开(公告)号：US20230412213A1
公开(公告)日：2023-12-21
申请号：US18195524
申请日：2023-05-10
Applicant: Rambus Inc.
Inventor： John W. POULTON , Frederick A. WARE , Carl W. WERNER
CPC classification number: H04B3/56 , H04L25/0272 , H04B10/50 , H03F3/24 , H04B3/54 , G06F13/4072
Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.
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公开(公告)号：US20230305915A1
公开(公告)日：2023-09-28
申请号：US18092556
申请日：2023-01-03
Applicant: Rambus Inc.
Inventor： Thomas J. GIOVANNINI , Catherine CHEN , Scott C. BEST , John Eric LINSTADT , Frederick A. WARE
CPC classification number: G06F11/079 , G06F11/073 , G06F11/0772 , G06F13/00 , G11C5/04 , G11C7/20 , G11C8/12 , G11C29/26 , G11C29/44
Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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4.发明申请公开(公告)号：US20230075057A1
公开(公告)日：2023-03-09
申请号：US17945863
申请日：2022-09-15
Applicant: Rambus Inc.
Inventor： Frederick A. WARE
IPC: G06F1/3287 , G06F1/3234 , G06F13/16 , G06F1/3293
Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.
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公开(公告)号：US20220374306A1
公开(公告)日：2022-11-24
申请号：US17840153
申请日：2022-06-14
Applicant: Rambus Inc.
Inventor： Angus William McLAREN , Robert A. HEATON , Aaron ALI , Frederick A. WARE
Abstract: A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.
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Patent Agency Ranking
公开(公告)号：US20210326204A1
公开(公告)日：2021-10-21
申请号：US17106663
申请日：2020-11-30
Applicant: Rambus Inc.
Inventor： Frederick A. WARE , Brent S. HAUKNESS , Lawrence LAI
IPC: G06F11/10
Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.
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7.发明申请公开(公告)号：US20200212960A1
公开(公告)日：2020-07-02
申请号：US16685861
申请日：2019-11-15
Applicant: Rambus Inc.
Inventor： John W. POULTON , Frederick A. WARE , Carl W. WERNER
Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.
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8.发明公开公开(公告)号：US20240184353A1
公开(公告)日：2024-06-06
申请号：US18535953
申请日：2023-12-11
Applicant: Rambus Inc.
Inventor： Frederick A. WARE
IPC: G06F1/3287 , G06F1/3234 , G06F1/3293 , G06F13/16
CPC classification number: G06F1/3287 , G06F1/3253 , G06F1/3278 , G06F1/3293 , G06F13/1694 , Y02D10/00
Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.
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公开(公告)号：US20230317196A1
公开(公告)日：2023-10-05
申请号：US18121220
申请日：2023-03-14
Applicant: Rambus Inc.
Inventor： John Eric LINSTADT , Frederick A. WARE
Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.
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公开(公告)号：US20220343992A1
公开(公告)日：2022-10-27
申请号：US17746674
申请日：2022-05-17
Applicant: Rambus Inc.
Inventor： John Eric LINSTADT , Frederick A. WARE
Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.
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