公开(公告)号：US20190238142A1

公开(公告)日：2019-08-01

申请号：US16242475

申请日：2019-01-08

Applicant: Rambus Inc.

Inventor： Jared L. ZERBE ,  Brian S. LEIBOWITZ ,  Hsuan-Jung SU ,  John Cronan EBLE, III ,  Barry William DALY ,  Lei LUO ,  Teva J. STONE ,  John WILSON ,  Jihong REN ,  Wayne D. DETTLOFF

IPC: H03L7/091 ,  H03L7/099 ,  H03L7/08 ,  G11C7/10 ,  H03L7/00 ,  H04L7/00 ,  H03K5/156 ,  H04L7/033 ,  G11C7/22

CPC classification number: H03L7/091 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  H03K5/1565 ,  H03L7/00 ,  H03L7/0802 ,  H03L7/099 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

公开(公告)号：US20250069644A1

公开(公告)日：2025-02-27

申请号：US18882372

申请日：2024-09-11

Applicant: Rambus Inc.

Inventor： Jared L. ZERBE ,  Frederick A. WARE

IPC: G11C11/4076 ,  G06F1/04 ,  G06F13/42 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C29/02 ,  H04L7/00

Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

公开(公告)号：US20240021236A1

公开(公告)日：2024-01-18

申请号：US18222808

申请日：2023-07-17

Applicant: Rambus Inc.

Inventor： Jared L. ZERBE ,  Frederick A. WARE

IPC: G11C11/4076 ,  G06F1/04 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F13/4243 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/04

Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

公开(公告)号：US20220130445A1

公开(公告)日：2022-04-28

申请号：US17521379

申请日：2021-11-08

Applicant: Rambus Inc.

Inventor： Jared L. ZERBE ,  Frederick A. WARE

IPC: G11C11/4076 ,  G06F1/04 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22

Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

公开(公告)号：US20200212917A1

公开(公告)日：2020-07-02

申请号：US16700008

申请日：2019-12-02

Applicant: Rambus Inc.

Inventor： Jared L. ZERBE ,  Brian S. LEIBOWITZ ,  Hsuan-Jung SU ,  John Cronan EBLE, III ,  Barry William DALY ,  Lei LUO ,  Teva J. STONE ,  John WILSON ,  Jihong REN ,  Wayne D. DETTLOFF

IPC: H03L7/091 ,  H03L7/099 ,  H03L7/08 ,  H04L7/033 ,  H04L7/00 ,  H03L7/00 ,  G11C7/22 ,  G11C7/10 ,  H03K5/156

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.