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    INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY
    3.
    发明申请
    INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY 有权
    包含频率变化检测电路的集成电路

    公开(公告)号：US20150333740A1

    公开(公告)日：2015-11-19

    申请号：US14808936

    申请日：2015-07-24

    Applicant: Rambus Inc.

    Inventor： Kambiz Kaviani ,  Kashinath Prabhu ,  Brian Hing-Kit Tsang ,  Jared L. Zerbe

    IPC: H03K3/012 ,  G11C7/22 ,  H03L7/24

    CPC classification number: H03K3/012 ,  G01R23/02 ,  G11C7/222 ,  H03K5/26 ,  H03L7/24

    Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

    Abstract translation: 描述了包括频率变化检测电路的集成电路（IC）的实施例。 一些实施例包括基于第一时钟信号产生第二时钟信号的第一电路，其中第一时钟信号具有第一时钟频率，并且其中第二时钟信号具有作为第一时钟频率的整数倍的第二时钟频率 。 实施例还包括通过使用第二时钟信号过采样第一时钟信号来获得采样的第二电路。 另外，实施例包括基于样本检测第一时钟频率的变化的第三电路。

    INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY
    4.
    发明申请
    INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY 有权
    包含频率变化检测电路的集成电路

    公开(公告)号：US20140070854A1

    公开(公告)日：2014-03-13

    申请号：US13839059

    申请日：2013-03-15

    Applicant: RAMBUS INC.

    Inventor： Kambiz Kaviani ,  Kashinath Prabhu ,  Brian Hing-Kit Tsang ,  Jared L. Zerbe

    IPC: H03K3/012

    CPC classification number: H03K3/012 ,  G01R23/02 ,  G11C7/222 ,  H03K5/26 ,  H03L7/24

    Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

    Abstract translation: 描述了包括频率变化检测电路的集成电路（IC）的实施例。 一些实施例包括基于第一时钟信号产生第二时钟信号的第一电路，其中第一时钟信号具有第一时钟频率，并且其中第二时钟信号具有作为第一时钟频率的整数倍的第二时钟频率 。 实施例还包括通过使用第二时钟信号过采样第一时钟信号来获得采样的第二电路。 另外，实施例包括基于样本检测第一时钟频率的变化的第三电路。

    CALIBRATION PROTOCOL FOR COMMAND AND ADDRESS BUS VOLTAGE REFERENCE IN LOW-SWING SINGLE-ENDED SIGNALING
    10.
    发明申请
    CALIBRATION PROTOCOL FOR COMMAND AND ADDRESS BUS VOLTAGE REFERENCE IN LOW-SWING SINGLE-ENDED SIGNALING 有权
    用于命令和地址的校准协议低电平单端信号中的总线电压参考

    公开(公告)号：US20140149618A1

    公开(公告)日：2014-05-29

    申请号：US14080724

    申请日：2013-11-14

    Applicant: Rambus Inc.

    Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Prabhu ,  Makarand Shirasgaonkar

    IPC: G06F13/16

    CPC classification number: G06F13/1668 ,  Y02D10/14

    Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

    Abstract translation: 单端接收器耦合到命令和地址（CA）总线的输入 - 输出（I / O）引脚。 接收器可配置双模式I / O支持，以低速摆幅模式和高摆幅模式操作CA总线。 接收器可配置为在高摆幅模式下在I / O引脚上接收第一个命令，响应于第一个命令启动从设备的低速摆动模式的校准，将从设备切换到操作状态 在低速摆动模式下，CA总线保持激活状态，并在低回转模式下在I / O引脚上接收第二个命令。

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