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    USING DYNAMIC BURSTS TO SUPPORT FREQUENCY-AGILE MEMORY INTERFACES
    5.
    发明申请
    USING DYNAMIC BURSTS TO SUPPORT FREQUENCY-AGILE MEMORY INTERFACES 有权
    使用动态脉冲串来支持频率记忆接口

    公开(公告)号：US20150177815A1

    公开(公告)日：2015-06-25

    申请号：US14416088

    申请日：2013-09-06

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Brian Hing-Kit Tsang ,  Barry William Daly

    IPC: G06F1/32

    CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/28 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

    Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a START memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

    Abstract translation: 所公开的实施例涉及支持动态突发以促进START存储器控制器和存储设备之间的频率敏捷通信的系统。 在操作期间，系统监视在存储器件和存储器控制器之间的接口处接收到的参考时钟信号。 在检测到从全速率到子速率的参考时钟信号中的频率变化时，接口以突发模式操作，其中数据通过由接口的部分断电的中间的低功率间隔分开的脉冲串传送。

    INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY
    7.
    发明申请
    INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY 有权
    包含频率变化检测电路的集成电路

    公开(公告)号：US20150333740A1

    公开(公告)日：2015-11-19

    申请号：US14808936

    申请日：2015-07-24

    Applicant: Rambus Inc.

    Inventor： Kambiz Kaviani ,  Kashinath Prabhu ,  Brian Hing-Kit Tsang ,  Jared L. Zerbe

    IPC: H03K3/012 ,  G11C7/22 ,  H03L7/24

    CPC classification number: H03K3/012 ,  G01R23/02 ,  G11C7/222 ,  H03K5/26 ,  H03L7/24

    Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

    Abstract translation: 描述了包括频率变化检测电路的集成电路（IC）的实施例。 一些实施例包括基于第一时钟信号产生第二时钟信号的第一电路，其中第一时钟信号具有第一时钟频率，并且其中第二时钟信号具有作为第一时钟频率的整数倍的第二时钟频率 。 实施例还包括通过使用第二时钟信号过采样第一时钟信号来获得采样的第二电路。 另外，实施例包括基于样本检测第一时钟频率的变化的第三电路。

    INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY
    9.
    发明申请
    INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY 有权
    包含频率变化检测电路的集成电路

    公开(公告)号：US20140070854A1

    公开(公告)日：2014-03-13

    申请号：US13839059

    申请日：2013-03-15

    Applicant: RAMBUS INC.

    Inventor： Kambiz Kaviani ,  Kashinath Prabhu ,  Brian Hing-Kit Tsang ,  Jared L. Zerbe

    IPC: H03K3/012

    CPC classification number: H03K3/012 ,  G01R23/02 ,  G11C7/222 ,  H03K5/26 ,  H03L7/24

    Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

    Abstract translation: 描述了包括频率变化检测电路的集成电路（IC）的实施例。 一些实施例包括基于第一时钟信号产生第二时钟信号的第一电路，其中第一时钟信号具有第一时钟频率，并且其中第二时钟信号具有作为第一时钟频率的整数倍的第二时钟频率 。 实施例还包括通过使用第二时钟信号过采样第一时钟信号来获得采样的第二电路。 另外，实施例包括基于样本检测第一时钟频率的变化的第三电路。

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