公开(公告)号：US20230025357A1

公开(公告)日：2023-01-26

申请号：US17847967

申请日：2022-06-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Genta WATANABE ,  Ken MATSUBARA ,  Tomoya SAITO ,  Akihiko KANDA ,  Koichi TAKEDA ,  Takahiro SHIMOI

IPC: G11C11/16

Abstract: A semiconductor device capable of changing a data programming process in a simple manner according to a situation is provided. The semiconductor device includes a plurality of memory cells, a programming circuit for supplying a programming current to the memory cell, and a power supply circuit for supplying power to the programming circuit. The power supply circuit includes a charge pump circuit for boosting the external power supply, a voltage of the external power supply according to the selection indication, and a selectable circuit capable of switching the boosted voltage boosted by the charge pump circuit. The control circuit further includes a control circuit for executing data programming processing by the programming circuit by switching the selection indication.

公开(公告)号：US20220382483A1

公开(公告)日：2022-12-01

申请号：US17746437

申请日：2022-05-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ken MATSUBARA ,  Takashi ITO ,  Takashi KURAFUJI ,  Yasuhiko TAITO ,  Tomoya SAITO ,  Akihiko KANDA

IPC: G06F3/06

Abstract: A semiconductor device includes a logic circuit, a memory, and a storage device. The storage device has a first special information storage region into which special information is written before a solder reflow process, a second special information storage region into which special information for updating is written after the solder reflow process, and a data storage region. The first special information storage region is constituted by a memory cell having a high reflow resistance and in which data is retained even after the solder reflow process. The second special information storage region and the data storage region are constituted by memory cells having a low reflow resistance and in which data may not be retained during the solder reflow process.

公开(公告)号：US20180233181A1

公开(公告)日：2018-08-16

申请号：US15845698

申请日：2017-12-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi IWASE ,  Ken MATSUBARA

IPC: G11C7/12 ,  G11C7/14

CPC classification number: G11C7/12 ,  G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32

Abstract: According to an embodiment, a semiconductor device includes a pre-charge transistor configured to supply a pre-charge voltage to a bit line, a sense amplifier configured to change a logic level of an output signal according to a result of a comparison between a drawing current of a storage element and a reference current, a clamp transistor disposed between the bit line BL and the sense amplifier, and a clamp voltage output transistor, in which a gate of the clamp voltage output transistor is connected to a gate of the clamp transistor, a source of the clamp voltage output transistor is connected to a back gate thereof, the pre-charge voltage is supplied to the source of the clamp voltage output transistor, a drain of the clamp voltage output transistor is connected to the gate thereof, and a ground voltage is supplied to a back gate of the clamp transistor.

公开(公告)号：US20180197609A1

公开(公告)日：2018-07-12

申请号：US15915823

申请日：2018-03-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ken MATSUBARA ,  Takashi IWASE ,  Satoru NAKANISHI

IPC: G11C16/08 ,  G11C16/04 ,  H03K3/356

CPC classification number: G11C16/08 ,  G11C16/0416 ,  G11C16/0433 ,  H03K3/356104

Abstract: In order to reduce the manufacturing cost, a flash memory includes a memory cell array formed by a plurality of memory cells arranged in a matrix shape; a plurality of word lines provided in each column of the memory cell array; a first word line driver that outputs a first voltage group to each of the word lines; and a second word line driver that outputs a second voltage group to each of the word lines together with the first word line driver.

公开(公告)号：US20170236587A1

公开(公告)日：2017-08-17

申请号：US15432228

申请日：2017-02-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ken MATSUBARA ,  Takashi IWASE ,  Satoru NAKANISHI

IPC: G11C16/08 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0416 ,  G11C16/0433 ,  H03K3/356104

Abstract: In order to reduce the manufacturing cost, a flash memory includes a memory cell array formed by a plurality of memory cells arranged in a matrix shape; a plurality of word lines provided in each column of the memory cell array; a first word line driver that outputs a first voltage group to each of the word lines; and a second word line driver that outputs a second voltage group to each of the word lines together with the first word line driver.

公开(公告)号：US20240126472A1

公开(公告)日：2024-04-18

申请号：US18397851

申请日：2023-12-27

Applicant: Renesas Electronics Corporation

Inventor： Ken MATSUBARA ,  Takashi ITO ,  Takashi KURAFUJI ,  Yasuhiko TAITO ,  Tomoya SAITO ,  Akihiko KANDA

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: A semiconductor device includes a logic circuit, a memory, and a storage device. The storage device has a first special information storage region into which special information is written before a solder reflow process, a second special information storage region into which special information for updating is written after the solder reflow process, and a data storage region. The first special information storage region is constituted by a memory cell having a high reflow resistance and in which data is retained even after the solder reflow process. The second special information storage region and the data storage region are constituted by memory cells having a low reflow resistance and in which data may not be retained during the solder reflow process.