公开(公告)号：US20180373651A1

公开(公告)日：2018-12-27

申请号：US15970083

申请日：2018-05-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi KURAFUJI

IPC: G06F13/16 ,  G11C16/06 ,  G06F9/48

CPC classification number: G06F13/1668 ,  G06F9/4812 ,  G11C7/1042 ,  G11C7/1075 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/22

Abstract: According to one embodiment, a memory controller is configured so that when the memory controller controls a writing/erasing process for a flash memory performed by a first or second master, the memory controller can prohibit, while the first master is performing the writing/erasing process for the flash memory, an interruption of the writing/erasing process in execution, the interruption resulting from access to the flash memory by the second master.

公开(公告)号：US20170278575A1

公开(公告)日：2017-09-28

申请号：US15466326

申请日：2017-03-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi KURAFUJI

IPC: G11C16/26 ,  G06F3/06 ,  G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  G11C16/20

CPC classification number: G11C16/26 ,  G06F3/0623 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0652 ,  G06F3/0655 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/16 ,  G11C16/20 ,  G11C16/28 ,  G11C16/3459

Abstract: An object of the present disclosure is to provide a semiconductor having high security. A semiconductor device includes: a memory region having a plurality of memory cells capable of storing data; a read circuit capable of switching a reference current reading method of reading data by comparing current flowing a memory cell to be read in the memory region with a reference current, and a complementary reading method of reading data by comparing currents flowing in first and second memory cells in which complementary data to be read in the memory region is stored; a register setting a security state; a mode controller setting a mode; and a control circuit controlling the reference current reading method and the complementary reading method of reading the data in the read circuit on the basis of a signal of setting a mode from the mode controller and a value of the register.

公开(公告)号：US20240126472A1

公开(公告)日：2024-04-18

申请号：US18397851

申请日：2023-12-27

Applicant: Renesas Electronics Corporation

Inventor： Ken MATSUBARA ,  Takashi ITO ,  Takashi KURAFUJI ,  Yasuhiko TAITO ,  Tomoya SAITO ,  Akihiko KANDA

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: A semiconductor device includes a logic circuit, a memory, and a storage device. The storage device has a first special information storage region into which special information is written before a solder reflow process, a second special information storage region into which special information for updating is written after the solder reflow process, and a data storage region. The first special information storage region is constituted by a memory cell having a high reflow resistance and in which data is retained even after the solder reflow process. The second special information storage region and the data storage region are constituted by memory cells having a low reflow resistance and in which data may not be retained during the solder reflow process.

公开(公告)号：US20160210070A1

公开(公告)日：2016-07-21

申请号：US14990668

申请日：2016-01-07

Applicant: Renesas Electronics Corporation

Inventor： Takashi KURAFUJI ,  Akira AWATANI

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0658 ,  G06F3/0679 ,  G06F3/0688

Abstract: An information processing apparatus according to the present invention includes: at least one flash memory including a data storage region that stores data and an erase count storage region that stores erase count data indicating the number of times that the data is erased in the data storage region; and a control circuit that is connected between a processor and the at least one flash memory. The control circuit allows changes of data stored in the data storage region by the processor and suppresses changes of the erase count data stored in the erase count storage region by the processor.

Abstract translation: 根据本发明的信息处理设备包括：至少一个闪速存储器，其包括存储数据的数据存储区域和擦除计数存储区域，其存储指示数据在数据存储区域中被擦除的次数的擦除计数数据 ; 以及连接在处理器和所述至少一个闪速存储器之间的控制电路。 控制电路允许由处理器改变存储在数据存储区域中的数据，并且通过处理器抑制存储在擦除计数存储区域中的擦除计数数据的改变。

公开(公告)号：US20200019341A1

公开(公告)日：2020-01-16

申请号：US16450294

申请日：2019-06-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi KURAFUJI ,  Satoshi YAMAMOTO

IPC: G06F3/06

Abstract: A master issues the valid data is specified when the data update processing is interrupted.The control unit 3 stores in the storage unit 2 the second update status flag 8_2, which indicates the update status of the first update status flag 8_1 and the second data 6_2, which indicate the update status of the first data 6_1, and the third update status flag 8_3, which indicates the update status of the valid indication flag 7. When the determination based on the valid instruction flag 7 is impossible, the usage data determination unit 4 determines which of the first data 6_1 and the second data 6_2 is valid based on the values of the first update status flag 8_1, the second update status flag 8_2, and the third update status flag 8_3.

公开(公告)号：US20180277214A1

公开(公告)日：2018-09-27

申请号：US15900516

申请日：2018-02-20

Applicant: Renesas Electronics Corporation

Inventor： Takashi KURAFUJI ,  Tomoya OGAWA ,  Yasuhiko TAITO

IPC: G11C16/04 ,  G11C16/28 ,  G11C16/10 ,  G11C16/14

CPC classification number: G11C16/0441 ,  G11C7/062 ,  G11C7/1006 ,  G11C7/1063 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/28 ,  G11C16/30 ,  G11C2207/063

Abstract: A storage device includes a data memory unit and a status memory unit. The data memory unit includes a pair of flash memory cells to be read by a complementary read mode, and 1-bit data is stored therein by the pair of flash memory cells. The status memory unit includes a flash memory cell to be read by a reference read mode, and a status flag is stored therein by the flash memory cell.

公开(公告)号：US20220382483A1

公开(公告)日：2022-12-01

申请号：US17746437

申请日：2022-05-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ken MATSUBARA ,  Takashi ITO ,  Takashi KURAFUJI ,  Yasuhiko TAITO ,  Tomoya SAITO ,  Akihiko KANDA

IPC: G06F3/06

Abstract: A semiconductor device includes a logic circuit, a memory, and a storage device. The storage device has a first special information storage region into which special information is written before a solder reflow process, a second special information storage region into which special information for updating is written after the solder reflow process, and a data storage region. The first special information storage region is constituted by a memory cell having a high reflow resistance and in which data is retained even after the solder reflow process. The second special information storage region and the data storage region are constituted by memory cells having a low reflow resistance and in which data may not be retained during the solder reflow process.

公开(公告)号：US20180240524A1

公开(公告)日：2018-08-23

申请号：US15956401

申请日：2018-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi KURAFUJI

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/20 ,  G11C16/16 ,  G11C16/10 ,  G06F3/06

CPC classification number: G11C16/26 ,  G06F3/0623 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0652 ,  G06F3/0655 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/16 ,  G11C16/20 ,  G11C16/28 ,  G11C16/3459

Abstract: An object of the present disclosure is to provide a semiconductor having high security. A semiconductor device includes: a memory region having a plurality of memory cells capable of storing data; a read circuit capable of switching a reference current reading method of reading data by comparing current flowing a memory cell to be read in the memory region with a reference current, and a complementary reading method of reading data by comparing currents flowing in first and second memory cells in which complementary data to be read in the memory region is stored; a register setting a security state; a mode controller setting a mode; and a control circuit controlling the reference current reading method and the complementary reading method of reading the data in the read circuit on the basis of a signal of setting a mode from the mode controller and a value of the register.

公开(公告)号：US20170357821A1

公开(公告)日：2017-12-14

申请号：US15582927

申请日：2017-05-01

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiko ASAI ,  Takashi KURAFUJI ,  Yoko KIMURA

IPC: G06F21/62 ,  G06F21/30 ,  G06F12/14

Abstract: To provide an information processing apparatus, a reading control method, and a computer readable storage medium that can improve the secrecy of information written in a secret area compared with the case of controlling access only by authentication, the information processing apparatus includes a nonvolatile memory (2) that has a secret area (6) where secret information is stored, an authentication controller (4) that authenticates access to the nonvolatile memory (2), a flag information storage unit (3) that stores flag information, and a memory controller (5) that controls access to the nonvolatile memory (2) by using the flag information stored in the flag information storage unit (3). The memory controller (5) allows reading of the secret information from the secret area (6) when a value of the flag information is a specified value and validity of access is authenticated by the authentication controller (4).