公开(公告)号：US20220382483A1

公开(公告)日：2022-12-01

申请号：US17746437

申请日：2022-05-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ken MATSUBARA ,  Takashi ITO ,  Takashi KURAFUJI ,  Yasuhiko TAITO ,  Tomoya SAITO ,  Akihiko KANDA

IPC: G06F3/06

Abstract: A semiconductor device includes a logic circuit, a memory, and a storage device. The storage device has a first special information storage region into which special information is written before a solder reflow process, a second special information storage region into which special information for updating is written after the solder reflow process, and a data storage region. The first special information storage region is constituted by a memory cell having a high reflow resistance and in which data is retained even after the solder reflow process. The second special information storage region and the data storage region are constituted by memory cells having a low reflow resistance and in which data may not be retained during the solder reflow process.

公开(公告)号：US20160012900A1

公开(公告)日：2016-01-14

申请号：US14859110

申请日：2015-09-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomoya OGAWA ,  Takashi ITO ,  Mitsuhiro TOMOEDA

IPC: G11C16/14 ,  G11C16/32

CPC classification number: G11C16/14 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  G11C16/32

Abstract: In a nonvolatile memory device provided in a semiconductor device, when data is erased based on a band-to-band tunneling scheme, supply of a boosted voltage to a memory cell (MC) to be erased is ended when a condition that an output voltage (VUCP) of a charge pump circuit has recovered to a predetermined reference voltage is satisfied and additionally a condition that a predetermined reference time has elapsed since start of supply of the boosted voltage (VUCP) to the memory cell (MC) to be erased is satisfied.

Abstract translation: 在设置在半导体器件中的非易失性存储器件中，当基于带 - 带隧穿方案擦除数据时，当要被擦除的存储器单元（MC）的提升电压向输出电压 已经恢复到预定参考电压的电荷泵电路（VUCP）被满足，并且另外从开始向被擦除的存储单元（MC）提供升压电压（VUCP）以来经过了预定基准时间的条件是 满意。

公开(公告)号：US20240126472A1

公开(公告)日：2024-04-18

申请号：US18397851

申请日：2023-12-27

Applicant: Renesas Electronics Corporation

Inventor： Ken MATSUBARA ,  Takashi ITO ,  Takashi KURAFUJI ,  Yasuhiko TAITO ,  Tomoya SAITO ,  Akihiko KANDA

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: A semiconductor device includes a logic circuit, a memory, and a storage device. The storage device has a first special information storage region into which special information is written before a solder reflow process, a second special information storage region into which special information for updating is written after the solder reflow process, and a data storage region. The first special information storage region is constituted by a memory cell having a high reflow resistance and in which data is retained even after the solder reflow process. The second special information storage region and the data storage region are constituted by memory cells having a low reflow resistance and in which data may not be retained during the solder reflow process.

公开(公告)号：US20140152379A1

公开(公告)日：2014-06-05

申请号：US14089489

申请日：2013-11-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshio FUJIMOTO ,  Takashi ITO

IPC: H01L49/02 ,  H02M3/07

CPC classification number: H01L28/60 ,  G11C5/145 ,  H01L23/5223 ,  H01L27/0222 ,  H01L27/11526 ,  H01L27/11573 ,  H01L28/86 ,  H01L28/90 ,  H01L29/94 ,  H01L2924/0002 ,  H02M3/073 ,  H01L2924/00

Abstract: There is provided a capacitor with a reduced layout area. A capacitor has an electrode EL1 formed by using a first polysilicon layer, an electrode EL2 formed by using a second polysilicon layer over the first polysilicon layer, and electrodes EL3 to EL6 formed by using second through fifth metal wiring layers over the second polysilicon layer. An N-type well and the electrode EL1 make up a capacitor element 11, the electrodes EL1, EL2 make up a capacitor element 12, and the electrodes EL3 to EL6 make up a capacitor element 13. The capacitor elements 11 to 13 are coupled in parallel between terminals T1, T2.

Abstract translation: 提供了具有减小的布局面积的电容器。 电容器具有通过使用第一多晶硅层形成的电极EL1，在第一多晶硅层上使用第二多晶硅层形成的电极EL2以及通过在第二多晶硅层上使用第二至第五金属布线层形成的电极EL3至EL6。 N型阱，电极EL1构成电容器元件11，电极EL1，EL2构成电容器元件12，电极EL3〜EL6构成电容器元件13.电容器元件11〜13耦合在 端子T1，T2之间平行。