公开(公告)号：US20230197827A1

公开(公告)日：2023-06-22

申请号：US18052382

申请日：2022-11-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Zhichao LIN ,  Koji OGATA ,  Yukio TAKAHASHI ,  Tomohiro IMAI ,  Tetsuya YOSHIDA

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L21/28 ,  H01L21/265

CPC classification number: H01L29/66348 ,  H01L29/7397 ,  H01L29/0638 ,  H01L29/0834 ,  H01L21/28185 ,  H01L21/28211 ,  H01L21/26513

Abstract: A gate electrode is formed inside a trench via a gate insulating film. The gate insulating film formed on a semiconductor substrate is removed. An insulating film is formed on the semiconductor substrate. A p-type base region is formed in the semiconductor substrate. An n-type emitter region is formed in the base region. Hydrogen annealing process is performed to the semiconductor substrate. A boundary between the base region and the emitter region is located at a position deeper than the insulating film formed between a side surface of the trench and the gate insulating film.

公开(公告)号：US20170358530A1

公开(公告)日：2017-12-14

申请号：US15665540

申请日：2017-08-01

Applicant: Renesas Electronics Corporation

Inventor： Yukio TAKAHASHI ,  Hitoshi MATSUURA

IPC: H01L23/525 ,  H01L29/739 ,  H01L29/06 ,  H01L27/02 ,  H01L29/40 ,  H01L23/522 ,  H01L29/66 ,  H01L21/66

CPC classification number: H01L23/5258 ,  H01L22/22 ,  H01L23/5228 ,  H01L27/0255 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/66348 ,  H01L29/7397

Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; a first insulating film formed in a convex shape and provided on the main surface of the semiconductor substrate; a first diffusion layer formed on the semiconductor substrate and provided to surround the first insulating film formed in a convex shape, the first diffusion layer being different in conductivity type from the semiconductor substrate; a first conductive layer formed so as to extend across the first insulating film formed in a convex shape, the first conductive layer forming a fuse element; and a second insulating film provided on the first conductive layer.

公开(公告)号：US20230411502A1

公开(公告)日：2023-12-21

申请号：US18185065

申请日：2023-03-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji OGATA ,  Tetsuya YOSHIDA ,  Yukio TAKAHASHI

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/66348 ,  H01L29/0696

Abstract: A semiconductor device includes an n-type semiconductor substrate, a trench, a gate electrode formed in the trench via the gate insulating film, a p-type base region formed in the semiconductor substrate, and an n-type emitter region formed in the base region. The trench extends in a Y direction, in a plan view. Adjacent ones of a plurality of emitter regions are formed to be spaced apart from each other by a distance, along the Y direction. The distance is wider than ⅕ of a width of each of the emitter regions in the Y direction and narrower than the width.

公开(公告)号：US20230064636A1

公开(公告)日：2023-03-02

申请号：US17870195

申请日：2022-07-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yukio TAKAHASHI

IPC: H01L23/522 ,  H01L21/304 ,  H01L21/768 ,  H01L23/532

Abstract: A first conductor pattern is formed on a semiconductor substrate of a scribing region via an insulating film. A plurality of second conductor patterns connected to the first conductor pattern are formed on the first conductor pattern. A third conductor pattern connected to the plurality of second conductor patterns is formed on the plurality of second conductor pattern. The scribing region is cut off in a Y direction by using a dicing blade so that a part of the scribing region is left in a chip region. In an X direction, a width of the dicing blade is narrower than each width of the first and second conductor patterns. After cutting off the scribing region, a part of the first conductor pattern, all or a part of at least one of the plurality of second conductor patterns, and a part of the third conductor pattern are left in the scribing region.

公开(公告)号：US20180350910A1

公开(公告)日：2018-12-06

申请号：US15971139

申请日：2018-05-04

Applicant: Renesas Electronics Corporation

Inventor： Shigeaki SAITO ,  Yoshito NAKAZAWA ,  Hitoshi MATSUURA ,  Yukio TAKAHASHI

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/739

CPC classification number: H01L29/0696 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/7397

Abstract: The reliability of a semiconductor device is improved. A contact trench for coupling a field plate and a field limiting ring situated at the corner part of a semiconductor device is formed of a first straight line part and a second straight line part arranged line symmetrically with respect to the crystal orientation . Respective one ends of the first straight line part and the second straight line part are coupled at the crystal orientation , and the first straight line part and the second straight line part are set to extend in different directions from the crystal orientation and the crystal orientation .

公开(公告)号：US20180308839A1

公开(公告)日：2018-10-25

申请号：US15904634

申请日：2018-02-26

Applicant: Renesas Electronics Corporation

Inventor： Yukio TAKAHASHI

IPC: H01L27/06 ,  H01L29/08 ,  H01L29/739 ,  H01L29/861

CPC classification number: H01L27/0664 ,  H01L29/0804 ,  H01L29/7397 ,  H01L29/861

Abstract: A semiconductor device and a method of manufacturing the same are provided so as to suppress an increase in the forward voltage of a first diode even if a driving signal is inputted to the gate electrode of an insulating gate bipolar transistor. An IGBT has a p-type body region. An anode region of the first diode has the same impurity region as the p-type body region of the IGBT. An anode region of a second diode is surrounded by an emitter groove and thus the anode region is separated from the p-type body region of the IGBT by the emitter groove.

公开(公告)号：US20170062336A1

公开(公告)日：2017-03-02

申请号：US15242788

申请日：2016-08-22

Applicant: Renesas Electronics Corporation

Inventor： Yukio TAKAHASHI ,  Hitoshi MATSUURA

IPC: H01L23/525 ,  H01L29/739 ,  H01L27/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L23/5258 ,  H01L22/22 ,  H01L23/5228 ,  H01L27/0255 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/66348 ,  H01L29/7397

Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; a first insulating film formed in a convex shape and provided on the main surface of the semiconductor substrate; a first diffusion layer formed on the semiconductor substrate and provided to surround the first insulating film formed in a convex shape, the first diffusion layer being different in conductivity type from the semiconductor substrate; a first conductive layer formed so as to extend across the first insulating film formed in a convex shape, the first conductive layer forming a fuse element; and a second insulating film provided on the first conductive layer.

Abstract translation: 半导体器件包括：具有主表面的半导体衬底; 形成为凸形并设置在所述半导体衬底的主表面上的第一绝缘膜; 第一扩散层，其形成在所述半导体基板上，并且设置成围绕形成为凸状的所述第一绝缘膜，所述第一扩散层的导电类型与所述半导体基板不同; 第一导电层，其形成为跨越形成为凸形的第一绝缘膜延伸，所述第一导电层形成熔丝元件; 以及设置在第一导电层上的第二绝缘膜。

公开(公告)号：US20180040612A1

公开(公告)日：2018-02-08

申请号：US15600729

申请日：2017-05-20

Applicant: Renesas Electronics Corporation

Inventor： Yukio TAKAHASHI ,  Hitoshi MATSUURA

IPC: H01L27/082 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L27/0825 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7397

Abstract: To improve current detection performance of a sense IGBT particularly in a low current region in a semiconductor device equipped with a main IGBT and the sense IGBT used for current detection of the main IGBT. At a peripheral portion located at an outermost periphery of an active region surrounded by a dummy region within a sense IGBT cell, an n+-type semiconductor region is formed over an upper surface of a well of a floating state adjacent to a trench gate electrode embedded into a trench at an upper surface of a semiconductor substrate and applied with a gate voltage.