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    Methods and circuits for asymmetric distribution of channel equalization between devices
    1.
    发明授权
    Methods and circuits for asymmetric distribution of channel equalization between devices 有权

    公开(公告)号：US10135647B2

    公开(公告)日：2018-11-20

    申请号：US15878149

    申请日：2018-01-23

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

    IPC: H04L25/03

    Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

    METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES
    2.
    发明申请
    METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES 有权
    用于设备之间的通道均衡化的不对称分配的方法和电路

    公开(公告)号：US20170054577A1

    公开(公告)日：2017-02-23

    申请号：US15233557

    申请日：2016-08-10

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

    IPC: H04L25/03

    CPC classification number: H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

    Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

    Abstract translation: 收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。 该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。 基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。

    Atomic-operation coalescing technique in multi-chip systems
    4.
    发明授权
    Atomic-operation coalescing technique in multi-chip systems 有权
    原子操作合并技术在多芯片系统中的应用

    公开(公告)号：US08838900B2

    公开(公告)日：2014-09-16

    申请号：US13914347

    申请日：2013-06-10

    Applicant: Rambus Inc.

    Inventor： Qi Lin ,  Liang Peng ,  Craig E. Hampel ,  Thomas J. Sheffler ,  Steven C. Woo ,  Bohuslav Rychlik

    IPC: G06F13/00 ,  G06F12/00 ,  G06F12/08 ,  G06F9/38 ,  G06F9/30

    CPC classification number: G06F12/00 ,  G06F9/3004 ,  G06F9/3834 ,  G06F12/0815

    Abstract: A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.

    Abstract translation: 高速缓存一致性协议在共享内存空间的多个处理器（或处理器核心）之间分配原子操作。 当包括修改存储在共享存储器空间中的数据的指令的原子操作被引导到不具有与数据相关联的地址的控制的第一处理器时，第一处理器发送包括指令的请求 修改数据到第二个处理器。 然后，已经具有对地址的控制的第二处理器修改数据。 此外，第一处理器可以立即进行另一个指令，而不是等待地址变得可用。

    ATOMIC-OPERATION COALESCING TECHNIQUE IN MULTI-CHIP SYSTEMS
    5.
    发明申请
    ATOMIC-OPERATION COALESCING TECHNIQUE IN MULTI-CHIP SYSTEMS 有权
    多芯片系统中的原理操作技术

    公开(公告)号：US20130275663A1

    公开(公告)日：2013-10-17

    申请号：US13914347

    申请日：2013-06-10

    Applicant: Rambus Inc.

    Inventor： Qi Lin ,  Liang Peng ,  Craig E. Hampel ,  Thomas J. Sheffler ,  Steven C. Woo ,  Bohusluv Rychlik

    IPC: G06F12/00

    CPC classification number: G06F12/00 ,  G06F9/3004 ,  G06F9/3834 ,  G06F12/0815

    Abstract: A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.

    Abstract translation: 缓存相干协议在共享内存空间的多个处理器（或处理器核心）之间分配原子操作。 当包括修改存储在共享存储器空间中的数据的指令的原子操作被引导到不具有与数据相关联的地址的控制的第一处理器时，第一处理器发送包括指令的请求 修改数据到第二个处理器。 然后，已经具有对地址的控制的第二处理器修改数据。 此外，第一处理器可以立即进行另一个指令，而不是等待地址变得可用。

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