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    SYNCHRONOUS WIRED-OR ACK STATUS FOR MEMORY WITH VARIABLE WRITE LATENCY
    2.
    发明申请
    SYNCHRONOUS WIRED-OR ACK STATUS FOR MEMORY WITH VARIABLE WRITE LATENCY 审中-公开

    公开(公告)号：US20200176617A1

    公开(公告)日：2020-06-04

    申请号：US16673431

    申请日：2019-11-04

    Applicant: Rambus Inc.

    Inventor： Yohan Frans ,  Simon Li ,  John Eric Linstadt ,  Jun Kim

    IPC: H01L31/0236 ,  G06F13/372 ,  G06F3/06 ,  G06F13/16 ,  G06F12/02

    Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

    PHASE CALIBRATION OF CLOCK SIGNALS
    3.
    发明申请
    PHASE CALIBRATION OF CLOCK SIGNALS 审中-公开

    公开(公告)号：US20190173661A1

    公开(公告)日：2019-06-06

    申请号：US16156868

    申请日：2018-10-10

    Applicant: Rambus Inc.

    Inventor： Marko Aleksic ,  Simon Li ,  Roxanne Vu

    IPC: H04L7/033 ,  H03L7/081 ,  H04L25/03 ,  H04L7/00

    CPC classification number: H04L7/033 ,  H03L7/081 ,  H04L7/0004 ,  H04L7/0079 ,  H04L7/0337 ,  H04L25/0292 ,  H04L25/03 ,  H04L25/03057 ,  H04L2025/03802

    Abstract: A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

    Phase calibration of clock signals
    4.
    发明授权
    Phase calibration of clock signals 有权

    公开(公告)号：US09755819B2

    公开(公告)日：2017-09-05

    申请号：US15176864

    申请日：2016-06-08

    Applicant: Rambus Inc.

    Inventor： Marko Aleksić ,  Simon Li ,  Roxanne Vu

    IPC: H04L25/40 ,  H04L7/033 ,  H04L7/00 ,  H04L25/03 ,  H03L7/081

    CPC classification number: H04L7/033 ,  H03L7/081 ,  H04L7/0004 ,  H04L7/0079 ,  H04L7/0337 ,  H04L25/03

    Abstract: A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

    Serial Link Receiver with Improved Bandwidth and Accurate Eye Monitor
    7.
    发明申请
    Serial Link Receiver with Improved Bandwidth and Accurate Eye Monitor 审中-公开

    公开(公告)号：US20200295974A1

    公开(公告)日：2020-09-17

    申请号：US16811353

    申请日：2020-03-06

    Applicant: Rambus Inc.

    Inventor： Marko Aleksic ,  Pravin Kumar Venkatesan ,  Simon Li ,  Nikhil Vaidya

    IPC: H04L25/03 ,  H03M13/21 ,  H03M13/00 ,  H04L1/00

    Abstract: A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

    PHASE CALIBRATION OF CLOCK SIGNALS
    9.
    发明申请
    PHASE CALIBRATION OF CLOCK SIGNALS 审中-公开

    公开(公告)号：US20180013544A1

    公开(公告)日：2018-01-11

    申请号：US15659394

    申请日：2017-07-25

    Applicant: Rambus Inc.

    Inventor： Marko Aleksic ,  Simon Li ,  Roxanne Vu

    IPC: H04L7/033 ,  H04L7/00 ,  H03L7/081 ,  H04L25/03

    CPC classification number: H04L7/033 ,  H03L7/081 ,  H04L7/0004 ,  H04L7/0079 ,  H04L7/0337 ,  H04L25/03

    Abstract: A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

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