公开(公告)号：US09825049B2

公开(公告)日：2017-11-21

申请号：US14997515

申请日：2016-01-16

Applicant: Renesas Electronics Corporation

Inventor： Naohiro Hosoda ,  Daisuke Okada ,  Kozo Katayama

IPC: H01L29/788 ,  H01L29/792 ,  H01L21/336 ,  H01L27/11568 ,  H01L27/115 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/42344 ,  H01L29/42364 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second insulating film formed between a memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, the second insulating film having a charge accumulating part therein. The second insulating film has a first film, a second film serving as a charge accumulating part disposed on the first film, and a third film disposed on the second film. The third film has a sidewall film positioned between the control gate electrode and the memory gate electrode and a deposited film positioned between the memory gate electrode and the semiconductor substrate. In this structure, the distance at a corner part of the second insulating film can be increased, and electric-field concentration can be reduced.

公开(公告)号：US20160379713A1

公开(公告)日：2016-12-29

申请号：US15152391

申请日：2016-05-11

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi ARIGANE ,  Daisuke Okada ,  Digh Hisamoto

IPC: G11C16/04 ,  H01L29/51 ,  H01L27/115 ,  G11C16/14 ,  H01L29/423

CPC classification number: G11C16/0466 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/511 ,  H01L29/518 ,  H01L29/792

Abstract: A first potential and a second potential lower than the first potential are applied to a first end of a memory gate electrode part of the nonvolatile memory and to a second end of the memory gate electrode part, respectively, so that a current is caused to flow in a direction in which the memory gate electrode part extends, then, a hole is injected from the memory gate electrode part into a charge accumulating part below it, therefore, an electron accumulated in the charge accumulating part is eliminated. By causing the current to flow through the memory gate electrode part of a memory cell region as described above, Joule heat can be generated to heat the memory cell. Consequently, in the erasing by a FN tunneling method in which the erasing characteristics degrade at a low temperature, the erasing speed can be improved by heating the memory gate electrode part.

Abstract translation: 低于第一电位的第一电势和第二电位被分别施加到非易失性存储器的存储栅电极部分的第一端和存储栅电极部分的第二端，使得电流流过 在存储栅电极部分延伸的方向上，从存储栅电极部分注入空穴到其下方的电荷累积部分，因此，积累在电荷累积部分中的电子被消除。 通过使电流流过如上所述的存储单元区域的存储栅电极部分，可以产生焦耳热以加热存储单元。 因此，在擦除特性在低温下劣化的FN隧穿法的擦除中，通过加热存储栅电极部分可以提高擦除速度。

公开(公告)号：US09257446B2

公开(公告)日：2016-02-09

申请号：US14548595

申请日：2014-11-20

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Daisuke Okada ,  Digh Hisamoto

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/66833 ,  H01L21/2815 ,  H01L21/28158 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/792

Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.

Abstract translation: 提供具有改善特性的非易失性存储器的半导体器件。 在半导体器件中，非易失性存储器在控制栅电极部分和存储栅电极部分之间具有高k绝缘膜（高介电常数膜），并且外围电路区域的晶体管具有高k /金属构造。 布置在控制栅电极部分和存储栅电极部分之间的高k绝缘膜松弛在控制栅电极部分一侧的存储栅电极部分的端部（拐角部分）的电场强度。 这导致电荷累积部分（氮化硅膜）中电荷的不均匀分布的减少和擦除精度的提高。

公开(公告)号：US20150187782A1

公开(公告)日：2015-07-02

申请号：US14584533

申请日：2014-12-29

Applicant: Renesas Electronics Corporation

Inventor： Hideaki Yamakoshi ,  Daisuke Okada

IPC: H01L27/115

CPC classification number: H01L27/11524 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/42324 ,  H01L29/42328

Abstract: Provided is a semiconductor device having improved performance. The semiconductor device includes the memory cells of a flash memory. Each of the memory cells includes a capacitor element for writing/erasing data having a gate electrode formed of a part of a floating gate electrode, and a MISFET for reading data having a gate electrode formed of another part of the floating gate electrode. The capacitor element for writing/erasing data has a p-type semiconductor region and an n-type semiconductor region which have opposite conductivity types. The length of the floating gate electrode in a gate length direction in the capacitor element for writing/erasing data is smaller than the length of the floating gate electrode in the gate length direction in the MISFET for reading data.

Abstract translation: 提供了具有改进的性能的半导体器件。 半导体器件包括闪速存储器的存储单元。 每个存储单元包括用于写入/擦除具有由浮置栅电极的一部分形成的栅电极的数据的电容器元件和用于读取具有由浮置栅电极的另一部分形成的栅电极的数据的MISFET。 用于写入/擦除数据的电容器元件具有具有相反导电类型的p型半导体区域和n型半导体区域。 用于写入/擦除数据的电容器元件中的栅极长度方向上的浮栅电极的长度小于用于读取数据的MISFET中的栅极长度方向上的浮栅电极的长度。

公开(公告)号：US10910394B2

公开(公告)日：2021-02-02

申请号：US16881484

申请日：2020-05-22

Applicant: Renesas Electronics Corporation

Inventor： Tsutomu Okazaki ,  Akira Kato ,  Kan Yasui ,  Kyoya Nitta ,  Digh Hisamoto ,  Yasushi Ishii ,  Daisuke Okada ,  Toshihiro Tanaka ,  Toshikazu Matsui

IPC: H01L27/1157 ,  H01L27/105 ,  H01L29/423 ,  H01L21/28 ,  G11C16/04 ,  H01L27/02 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66 ,  H01L29/792 ,  H01L29/06 ,  H01L29/51

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

公开(公告)号：US10692878B2

公开(公告)日：2020-06-23

申请号：US16552524

申请日：2019-08-27

Applicant: Renesas Electronics Corporation

Inventor： Tsutomu Okazaki ,  Akira Kato ,  Kan Yasui ,  Kyoya Nitta ,  Digh Hisamoto ,  Yasushi Ishii ,  Daisuke Okada ,  Toshihiro Tanaka ,  Toshikazu Matsui

IPC: H01L27/1157 ,  H01L27/105 ,  H01L29/423 ,  H01L21/28 ,  G11C16/04 ,  H01L27/02 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66 ,  H01L29/792 ,  H01L29/06 ,  H01L29/51

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

公开(公告)号：US10141324B2

公开(公告)日：2018-11-27

申请号：US15581576

申请日：2017-04-28

Applicant: Renesas Electronics Corporation

Inventor： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L29/51 ,  H01L27/02 ,  H01L21/28

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

公开(公告)号：US09589638B2

公开(公告)日：2017-03-07

申请号：US15152391

申请日：2016-05-11

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Daisuke Okada ,  Digh Hisamoto

IPC: G11C16/04 ,  G11C16/14 ,  H01L29/423 ,  H01L27/115 ,  H01L29/51 ,  G11C16/34

CPC classification number: G11C16/0466 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/511 ,  H01L29/518 ,  H01L29/792

Abstract: A first potential and a second potential lower than the first potential are applied to a first end of a memory gate electrode part of the nonvolatile memory and to a second end of the memory gate electrode part, respectively, so that a current is caused to flow in a direction in which the memory gate electrode part extends, then, a hole is injected from the memory gate electrode part into a charge accumulating part below it, therefore, an electron accumulated in the charge accumulating part is eliminated. By causing the current to flow through the memory gate electrode part of a memory cell region as described above, Joule heat can be generated to heat the memory cell. Consequently, in the erasing by a FN tunneling method in which the erasing characteristics degrade at a low temperature, the erasing speed can be improved by heating the memory gate electrode part.

Abstract translation: 低于第一电位的第一电势和第二电位被分别施加到非易失性存储器的存储栅电极部分的第一端和存储栅电极部分的第二端，使得电流流过 在存储栅电极部分延伸的方向上，从存储栅电极部分注入空穴到其下方的电荷累积部分，因此，积累在电荷累积部分中的电子被消除。 通过使电流流过如上所述的存储单元区域的存储栅电极部分，可以产生焦耳热以加热存储单元。 因此，在擦除特性在低温下劣化的FN隧穿法的擦除中，通过加热存储栅电极部分可以提高擦除速度。

公开(公告)号：US09640546B2

公开(公告)日：2017-05-02

申请号：US14609659

申请日：2015-01-30

Applicant: Renesas Electronics Corporation

Inventor： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC: H01L29/792 ,  H01L27/1157 ,  H01L27/105 ,  H01L29/423 ,  G11C16/04 ,  H01L21/28 ,  H01L27/02 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66

CPC classification number: H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

公开(公告)号：US09515082B2

公开(公告)日：2016-12-06

申请号：US14664493

申请日：2015-03-20

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Digh Hisamoto ,  Daisuke Okada

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L21/762

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: A memory gate is formed of a first memory gate including a second gate insulating film made of a second insulating film and a first memory gate electrode, and a second memory gate including a third gate insulating film made of a third insulating film and a second memory gate electrode. In addition, the lower surface of the second memory gate electrode is located lower in level than the lower surface of the first memory gate electrode. As a result, during an erase operation, an electric field is concentrated on the corner portion of the first memory gate electrode which is located closer to a selection gate and a semiconductor substrate and on the corner portion of the second memory gate electrode which is located closer to the first memory gate and the semiconductor substrate. This allows easy injection of holes into each of the second and third insulating films.

Abstract translation: 存储栅极由包括由第二绝缘膜和第一存储栅电极构成的第二栅绝缘膜的第一存储栅形成，以及包括由第三绝缘膜和第二存储器构成的第三栅绝缘膜的第二存储栅 栅电极。 此外，第二存储栅电极的下表面位于比第一存储栅电极的下表面更低的电平。 结果，在擦除操作期间，电场集中在位于更靠近选择栅极和半导体衬底的位于第一存储栅电极的角部上，并且位于位于第二存储栅电极的拐角部分 更靠近第一存储器栅极和半导体衬底。 这允许容易地将孔注入到每个第二和第三绝缘膜中。