公开(公告)号：US08217463B2

公开(公告)日：2012-07-10

申请号：US13021403

申请日：2011-02-04

Applicant: Rohit Pal ,  Michael Hargrove ,  Frank Bin Yang

Inventor： Rohit Pal ,  Michael Hargrove ,  Frank Bin Yang

IPC: H01L29/66

CPC classification number: H01L29/66651 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28247 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.

Abstract translation: 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 制造半导体器件的方法包括提供具有有源区和浅沟槽隔离（STI）区的半导体衬底。 在有源区上形成外延层，以在有源区/ STI区界面上的边界中限定一个横向伸出部分。 形成具有覆盖在半导体衬底上的第一栅叠层形成层的栅叠层。 第一栅极堆叠形成层包括定向沉积以形成刚好在横向突出部分下方的变薄的断裂部分的非保形层的金属栅极形成材料。 在形成栅极堆叠的步骤之后，非共形层的第一部分在栅极堆叠中并且第二部分被暴露。 减薄断裂部分在随后的蚀刻化学过程中至少部分地隔离第一和第二部分。

公开(公告)号：US07670934B1

公开(公告)日：2010-03-02

申请号：US12359764

申请日：2009-01-26

Applicant: Rohit Pal ,  Frank Bin Yang

Inventor： Rohit Pal ,  Frank Bin Yang

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84

Abstract: Methods of fabricating a semiconductor device on and in a semiconductor substrate having a first region and a second region are provided. In accordance with an exemplary embodiment of the invention, a method comprises forming a first gate stack overlying the first region and a second gate stack overlying the second region, etching into the substrate first recesses and second recesses, the first recesses aligned at least to the first gate stack in the first region, and the second recesses aligned at least to the second gate stack in the second region, epitaxially growing a first stress-inducing monocrystalline material in the first and second recesses, removing the first stress-inducing monocrystalline material from the first recesses, and epitaxially growing a second stress-inducing monocrystalline material in the first recesses, wherein the second stress-inducing monocrystalline material has a composition different from the first stress-inducing monocrystalline material.

Abstract translation: 提供了在具有第一区域和第二区域的半导体衬底上和半导体衬底中制造半导体器件的方法。 根据本发明的示例性实施例，一种方法包括形成覆盖第一区域的第一栅极堆叠和覆盖第二区域的第二栅极堆叠，蚀刻到衬底中的第一凹陷和第二凹槽，第一凹陷至少对准 第一栅极堆叠在第一区域中，并且第二凹陷至少对准第二区域中的第二栅极堆叠，在第一和第二凹槽中外延生长第一应力诱导单晶材料，从第一和第二凹槽中去除第一应力诱导单晶材料 第一凹陷，并且在第一凹陷中外延生长第二应力诱导单晶材料，其中第二应力诱导单晶材料具有不同于第一应力诱导单晶材料的组成。

公开(公告)号：US08293609B2

公开(公告)日：2012-10-23

申请号：US13355221

申请日：2012-01-20

Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

公开(公告)号：US08148750B2

公开(公告)日：2012-04-03

申请号：US13052969

申请日：2011-03-21

Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

IPC: H01L21/02

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

公开(公告)号：US07960229B2

公开(公告)日：2011-06-14

申请号：US12100598

申请日：2008-04-10

Applicant: Frank Bin Yang ,  Rohit Pal ,  Scott Luning

Inventor： Frank Bin Yang ,  Rohit Pal ,  Scott Luning

IPC: H01L21/336

CPC classification number: H01L29/66628 ,  H01L29/66772 ,  H01L29/78618

Abstract: A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.

Abstract translation: 提供了具有减小的栅极高度的金属氧化物半导体晶体管器件。 器件的一个实施例包括具有半导体材料层的衬底，覆盖半导体材料层的栅极结构以及形成在与栅极结构相邻的半导体材料中的源极/漏极凹槽，使得剩余的半导体材料位于 源极/漏极凹槽。 器件还包括在剩余半导体材料中形成的浅源极/漏极注入区域，以及在源极/漏极凹槽中外延生长的原位掺杂的半导体材料。

公开(公告)号：US07994014B2

公开(公告)日：2011-08-09

申请号：US12249570

申请日：2008-10-10

Applicant: Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

Inventor： Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02636 ,  H01L29/045 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabricated in accordance with the processes disclosed herein includes a layer of semiconductor material and a gate structure overlying the layer of semiconductor material. A channel region is formed in the layer of semiconductor material, the channel region underlying the gate structure. The semiconductor device also includes source and drain regions in the layer of semiconductor material, wherein the channel region is located between the source and drain regions. Moreover, the semiconductor device includes facet-shaped silicide contact areas overlying the source and drain regions.

Abstract translation: 所公开的主题涉及半导体晶体管器件和相关的制造技术，其可以用于形成相对于常规硅化物触点具有增加的有效尺寸的硅化物触点。 根据本文公开的方法制造的半导体器件包括覆盖半导体材料层的半导体材料层和栅极结构。 沟道区形成在半导体材料层中，栅极结构下方的沟道区。 半导体器件还包括半导体材料层中的源区和漏区，其中沟道区位于源区和漏区之间。 此外，半导体器件包括覆盖源极和漏极区域的面形硅化物接触区域。

公开(公告)号：US07939852B2

公开(公告)日：2011-05-10

申请号：US12176835

申请日：2008-07-21

Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

IPC: H01L31/0328

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

公开(公告)号：US08076209B2

公开(公告)日：2011-12-13

申请号：US12771948

申请日：2010-04-30

Applicant: Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

Inventor： Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

IPC: H01L21/336

CPC classification number: H01L29/7847 ,  H01L29/66636

Abstract: Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, etching recesses into the substrate using the gate electrode as an etch mask, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.

Abstract translation: 提供了用于形成包括含硅衬底的半导体器件的方法。 一种示例性方法包括沉积覆盖含硅衬底的多晶硅层，使多晶硅层非晶化，蚀刻非晶化多晶硅层以形成栅电极，使用栅电极作为蚀刻掩模将凹陷蚀刻到衬底中，沉积应力诱导 覆盖栅极电极，退火含硅衬底以使栅电极重结晶，去除应力诱导层，以及在凹槽中外延生长杂质掺杂的含硅区域。

公开(公告)号：US08026539B2

公开(公告)日：2011-09-27

申请号：US12388094

申请日：2009-02-18

Applicant: Michael Hargrove ,  Frank Bin Yang ,  Rohit Pal

Inventor： Michael Hargrove ,  Frank Bin Yang ,  Rohit Pal

IPC: H01L29/76

CPC classification number: H01L21/28088 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.

Abstract translation: 提供了用于形成包括半导体衬底的半导体器件的方法。 根据示例性实施例，一种方法包括以下步骤：形成覆盖在半导体衬底上的高k电介质层，形成覆盖在高k电介质层上的包含金属的栅极层，形成掺杂的含硅覆盖层 含金属的栅极层，以及沉积覆盖掺杂的含硅覆盖层的含硅栅极层。

公开(公告)号：US20100207176A1

公开(公告)日：2010-08-19

申请号：US12388094

申请日：2009-02-18

Applicant: Michael Hargrove ,  Frank Bin Yang ,  Rohit Pal

Inventor： Michael Hargrove ,  Frank Bin Yang ,  Rohit Pal

IPC: H01L29/78 ,  H01L21/4763

CPC classification number: H01L21/28088 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.

Abstract translation: 提供了用于形成包括半导体衬底的半导体器件的方法。 根据示例性实施例，一种方法包括以下步骤：形成覆盖在半导体衬底上的高k电介质层，形成覆盖在高k电介质层上的包含金属的栅极层，形成掺杂的含硅覆盖层 含金属的栅极层，以及沉积覆盖掺杂的含硅覆盖层的含硅栅极层。