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公开(公告)号：US20130071762A1
公开(公告)日：2013-03-21
申请号：US13610951
申请日：2012-09-12
申请人： Ryota TAJIMA , Shunpei Yamazaki , Teppei Oguni , Takeshi Osada , Shinya Sasagawa , Kazutaka Kuriki
发明人： Ryota TAJIMA , Shunpei Yamazaki , Teppei Oguni , Takeshi Osada , Shinya Sasagawa , Kazutaka Kuriki
CPC分类号： H01M4/133 , B82Y30/00 , H01M4/134 , H01M4/1395 , H01M4/366 , H01M4/386 , H01M4/625 , H01M10/0525 , H01M10/465 , Y02E60/122 , Y02T10/7011
摘要： A power storage device which has high charge/discharge capacity and less deterioration in battery characteristics due to charge/discharge and can perform charge/discharge at high speed is provided. A power storage device includes a negative electrode. The negative electrode includes a current collector and an active material layer provided over the current collector. The active material layer includes a plurality of protrusions protruding from the current collector and a graphene provided over the plurality of protrusions. Axes of the plurality of protrusions are oriented in the same direction. A common portion may be provided between the current collector and the plurality of protrusions.
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公开(公告)号：US08822088B2
公开(公告)日：2014-09-02
申请号：US13610951
申请日：2012-09-12
申请人： Ryota Tajima , Shunpei Yamazaki , Teppei Oguni , Takeshi Osada , Shinya Sasagawa , Kazutaka Kuriki
发明人： Ryota Tajima , Shunpei Yamazaki , Teppei Oguni , Takeshi Osada , Shinya Sasagawa , Kazutaka Kuriki
IPC分类号： H01M4/36 , H01M10/0525 , H01M4/62 , B82Y30/00 , H01M4/1395 , H01M4/38 , H01M4/134 , H01M10/46
CPC分类号： H01M4/133 , B82Y30/00 , H01M4/134 , H01M4/1395 , H01M4/366 , H01M4/386 , H01M4/625 , H01M10/0525 , H01M10/465 , Y02E60/122 , Y02T10/7011
摘要： A power storage device which has high charge/discharge capacity and less deterioration in battery characteristics due to charge/discharge and can perform charge/discharge at high speed is provided. A power storage device includes a negative electrode. The negative electrode includes a current collector and an active material layer provided over the current collector. The active material layer includes a plurality of protrusions protruding from the current collector and a graphene provided over the plurality of protrusions. Axes of the plurality of protrusions are oriented in the same direction. A common portion may be provided between the current collector and the plurality of protrusions.
摘要翻译： 具有充电/放电容量高，蓄电池特性劣化少的蓄电装置，能够高速进行充放电。 蓄电装置包括负极。 负极包括设置在集电体上方的集电体和活性物质层。 活性物质层包括从集电体突出的多个突起和设置在多个突起上的石墨烯。 多个突起的轴线朝向相同的方向。 在集电体和多个突起之间可以设置公共部分。
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公开(公告)号：US08834989B2
公开(公告)日：2014-09-16
申请号：US13295278
申请日：2011-11-14
IPC分类号： H01L21/00 , H01L29/786 , H01L27/12 , H01L29/66
CPC分类号： H01L27/12 , H01L29/66757 , H01L29/78675 , Y10T428/24421
摘要： An object is to provide a semiconductor device with improved reliability and for which a defect due to an end portion of a semiconductor layer provided in an island-shape is prevented, and a manufacturing method thereof. A structure includes an island-shaped semiconductor layer provided over a substrate, an insulating layer provided over a top surface and a side surface of the island-shaped semiconductor layer, and a gate electrode provided over the island-shaped semiconductor layer with the insulating layer interposed therebetween. In the insulating layer provided to be in contact with the island-shaped semiconductor layer, a region that is in contact with the side surface of the island-shaped semiconductor layer is made to have a lower dielectric constant than a region over the top surface of the island-shaped semiconductor layer.
摘要翻译： 本发明的目的是提供一种可靠性提高的半导体器件及其制造方法，该半导体器件具有提高的岛状半导体层的端部的缺陷。 一种结构包括设置在基板上的岛状半导体层，设置在岛状半导体层的顶表面和侧表面上的绝缘层以及设置在岛状半导体层上的绝缘层的栅电极 插入其间。 在与岛状半导体层接触的绝缘层中，使与岛状半导体层的侧面接触的区域的介电常数比上述表面的区域低 岛状半导体层。
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公开(公告)号：US20080128703A1
公开(公告)日：2008-06-05
申请号：US11949186
申请日：2007-12-03
IPC分类号： H01L29/04 , H01L21/336
CPC分类号： H01L27/12 , H01L29/66757 , H01L29/78675 , Y10T428/24421
摘要： An object is to provide a semiconductor device with improved reliability and for which a defect due to an end portion of a semiconductor layer provided in an island-shape is prevented, and a manufacturing method thereof. A structure includes an island-shaped semiconductor layer provided over a substrate, an insulating layer provided over a top surface and a side surface of the island-shaped semiconductor layer, and a gate electrode provided over the island-shaped semiconductor layer with the insulating layer interposed therebetween. In the insulating layer provided to be in contact with the island-shaped semiconductor layer, a region that is in contact with the side surface of the island-shaped semiconductor layer is made to have a lower dielectric constant than a region over the top surface of the island-shaped semiconductor layer.
摘要翻译： 本发明的目的是提供一种可靠性提高的半导体器件及其制造方法，该半导体器件具有提高的岛状半导体层的端部的缺陷。 一种结构包括设置在基板上的岛状半导体层，设置在岛状半导体层的顶表面和侧表面上的绝缘层以及设置在岛状半导体层上的绝缘层的栅电极 插入其间。 在与岛状半导体层接触的绝缘层中，使与岛状半导体层的侧面接触的区域的介电常数比上述表面的区域低 岛状半导体层。
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公开(公告)号：US08809992B2
公开(公告)日：2014-08-19
申请号：US13356012
申请日：2012-01-23
申请人： Shunpei Yamazaki , Atsuo Isobe , Toshihiko Saito , Takehisa Hatano , Hideomi Suzawa , Shinya Sasagawa , Junichi Koezuka , Yuichi Sato , Shinji Ohno
发明人： Shunpei Yamazaki , Atsuo Isobe , Toshihiko Saito , Takehisa Hatano , Hideomi Suzawa , Shinya Sasagawa , Junichi Koezuka , Yuichi Sato , Shinji Ohno
IPC分类号： H01L29/786
CPC分类号： H01L29/66969 , H01L21/02488 , H01L21/02565 , H01L27/1225 , H01L29/786 , H01L29/78606 , H01L29/7869
摘要： A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.
摘要翻译： 提供了包括氧化物半导体并且具有良好的电特性的半导体器件。 在半导体器件中，在衬底上形成氧化物半导体膜和绝缘膜。 氧化物半导体膜的侧面与绝缘膜接触。 氧化物半导体膜包括沟道形成区域和包含掺杂剂的区域，沟道形成区域夹在其间。 栅极绝缘膜与氧化物半导体膜形成并接触。 在栅绝缘膜上形成具有侧壁绝缘膜的栅电极。 源电极和漏电极形成为与氧化物半导体膜和绝缘膜接触。
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公开(公告)号：US08653520B2
公开(公告)日：2014-02-18
申请号：US13021343
申请日：2011-02-04
申请人： Shunpei Yamazaki , Teruyuki Fujii , Ryota Imahayashi , Shinya Sasagawa , Motomu Kurata , Fumika Taguchi
发明人： Shunpei Yamazaki , Teruyuki Fujii , Ryota Imahayashi , Shinya Sasagawa , Motomu Kurata , Fumika Taguchi
CPC分类号： H01L27/0688 , G11C16/0416 , G11C16/0433 , G11C16/28 , H01L27/1052 , H01L27/11521 , H01L27/11551 , H01L27/1156 , H01L27/1207 , H01L27/1225
摘要： An object is to provide a semiconductor device having a novel structure in which a transistor including an oxide semiconductor and a transistor including a semiconductor material other than an oxide semiconductor are stacked. The semiconductor device includes a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer. In the semiconductor device, the first transistor includes a first channel formation region, the second transistor includes a second channel formation region, the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region, and the insulating layer includes a surface whose root-mean-square surface roughness is less than or equal to 1 nm.
摘要翻译： 目的是提供一种具有新颖结构的半导体器件，其中包括氧化物半导体的晶体管和包括氧化物半导体之外的半导体材料的晶体管被堆叠。 该半导体器件包括第一晶体管，第一晶体管上的绝缘层和绝缘层上的第二晶体管。 在半导体器件中，第一晶体管包括第一沟道形成区，第二晶体管包括第二沟道形成区，第一沟道形成区包括与第二沟道形成区的半导体材料不同的半导体材料，绝缘层 包括均方根表面粗糙度小于或等于1nm的表面。
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公开(公告)号：US08624400B2
公开(公告)日：2014-01-07
申请号：US12840442
申请日：2010-07-21
IPC分类号： H01L23/52 , H01L29/786
CPC分类号： H01L29/41733 , H01L21/76804 , H01L21/76805 , H01L23/485 , H01L27/124 , H01L2924/0002 , H01L2924/00
摘要： A technique of manufacturing a semiconductor device in which etching in formation of a contact hole can be easily controlled is proposed. A semiconductor device includes at least a semiconductor layer formed over an insulating surface; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; and a conductive layer formed over the second insulating layer connected to the semiconductor layer via an opening which is formed at least in the semiconductor layer and the second insulating layer and partially exposes the insulating surface. The conductive layer is electrically connected to the semiconductor layer at the side surface of the opening which is formed in the semiconductor layer.
摘要翻译： 提出了可以容易地控制形成接触孔的蚀刻的半导体器件的制造技术。 半导体器件至少包括形成在绝缘表面上的半导体层; 形成在所述半导体层上的第一绝缘层; 形成在所述第一绝缘层上的栅电极; 形成在所述栅电极上的第二绝缘层; 以及形成在所述第二绝缘层之上的导电层，所述导电层经由至少在所述半导体层和所述第二绝缘层中形成并且部分地暴露所述绝缘表面的开口连接到所述半导体层。 导电层在形成于半导体层的开口的侧面与半导体层电连接。
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公开(公告)号：US08492840B2
公开(公告)日：2013-07-23
申请号：US13008285
申请日：2011-01-18
申请人： Shunpei Yamazaki , Hiromichi Godo , Hideomi Suzawa , Shinya Sasagawa , Motomu Kurata , Mayumi Mikami
发明人： Shunpei Yamazaki , Hiromichi Godo , Hideomi Suzawa , Shinya Sasagawa , Motomu Kurata , Mayumi Mikami
IPC分类号： H01L27/12
CPC分类号： H01L29/7869
摘要： An object is to provide a semiconductor device including an oxide semiconductor, which maintains favorable characteristics and achieves miniaturization. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, in which the source electrode and the drain electrode each include a first conductive layer, and a second conductive layer having a region which extends in a channel length direction from an end portion of the first conductive layer.
摘要翻译： 本发明的目的是提供一种包含氧化物半导体的半导体器件，其保持有利的特性并实现小型化。 半导体器件包括与氧化物半导体层接触的氧化物半导体层，源极和漏电极，与氧化物半导体层重叠的栅电极，以及设置在氧化物半导体层和栅电极之间的栅极绝缘层， 其中源电极和漏极各自包括第一导电层，以及具有从第一导电层的端部在沟道长度方向上延伸的区域的第二导电层。
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公开(公告)号：US08067772B2
公开(公告)日：2011-11-29
申请号：US11949186
申请日：2007-12-03
IPC分类号： H01L29/04
CPC分类号： H01L27/12 , H01L29/66757 , H01L29/78675 , Y10T428/24421
摘要： An object is to provide a semiconductor device with improved reliability and for which a defect due to an end portion of a semiconductor layer provided in an island-shape is prevented, and a manufacturing method thereof. A structure includes an island-shaped semiconductor layer provided over a substrate, an insulating layer provided over a top surface and a side surface of the island-shaped semiconductor layer, and a gate electrode provided over the island-shaped semiconductor layer with the insulating layer interposed therebetween. In the insulating layer provided to be in contact with the island-shaped semiconductor layer, a region that is in contact with the side surface of the island-shaped semiconductor layer is made to have a lower dielectric constant than a region over the top surface of the island-shaped semiconductor layer.
摘要翻译： 本发明的目的是提供一种可靠性提高的半导体器件及其制造方法，该半导体器件具有提高的岛状半导体层的端部的缺陷。 一种结构包括设置在基板上的岛状半导体层，设置在岛状半导体层的顶表面和侧表面上的绝缘层以及设置在岛状半导体层上的绝缘层的栅电极 插入其间。 在与岛状半导体层接触的绝缘层中，使与岛状半导体层的侧面接触的区域的介电常数比上述表面的区域低 岛状半导体层。
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公开(公告)号：US07763981B2
公开(公告)日：2010-07-27
申请号：US12046817
申请日：2008-03-12
IPC分类号： H01L23/52
CPC分类号： H01L29/41733 , H01L21/76804 , H01L21/76805 , H01L23/485 , H01L27/124 , H01L2924/0002 , H01L2924/00
摘要： A technique of manufacturing a semiconductor device in which etching in formation of a contact hole can be easily controlled is proposed. A semiconductor device includes at least a semiconductor layer formed over an insulating surface; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; and a conductive layer formed over the second insulating layer connected to the semiconductor layer via an opening which is formed at least in the semiconductor layer and the second insulating layer and partially exposes the insulating surface. The conductive layer is electrically connected to the semiconductor layer at the side surface of the opening which is formed in the semiconductor layer.
摘要翻译： 提出了可以容易地控制形成接触孔的蚀刻的半导体器件的制造技术。 半导体器件至少包括形成在绝缘表面上的半导体层; 形成在所述半导体层上的第一绝缘层; 形成在所述第一绝缘层上的栅电极; 形成在所述栅电极上的第二绝缘层; 以及形成在所述第二绝缘层之上的导电层，所述导电层经由至少在所述半导体层和所述第二绝缘层中形成并且部分地暴露所述绝缘表面的开口连接到所述半导体层。 导电层在形成于半导体层的开口的侧面与半导体层电连接。
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