公开(公告)号：US11869896B2

公开(公告)日：2024-01-09

申请号：US17368200

申请日：2021-07-06

Applicant: Samsung Display Co., Ltd.

Inventor： Woo Bin Lee ,  Seok Hwan Bang ,  Seung Sok Son ,  Woo Geun Lee ,  Soo Jung Chae

IPC: H01L27/12 ,  H10K59/121 ,  H10K77/10 ,  H10K102/00

CPC classification number: H01L27/1222 ,  H01L27/1218 ,  H01L27/1225 ,  H10K59/1213 ,  H10K77/111 ,  H10K2102/311

Abstract: A display device includes a substrate and a transistor disposed on the substrate and including a semiconductor layer, wherein the semiconductor layer includes a mesh structure, and wherein a plurality of openings are formed in the semiconductor layer.

公开(公告)号：US09893203B2

公开(公告)日：2018-02-13

申请号：US15246366

申请日：2016-08-24

Applicant: Samsung Display Co., Ltd.

Inventor： Seok Hwan Bang ,  Sook-Hwan Ban ,  Hyung Jun Kim ,  Woo Geun Lee ,  Hyeon Jun Lee

IPC: H01L29/786 ,  H01L27/12 ,  H01L27/32 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: H01L29/7869 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1262 ,  H01L27/3248 ,  H01L27/3276 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/78696

Abstract: One or more exemplary embodiments disclose a thin film transistor array panel and a manufacturing method thereof including a substrate, a gate line on the substrate, the gate line including a gate electrode, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, and the semiconductor layer including an oxide semiconductor, a data wire layer above the semiconductor layer, the data wire layer including a data line, a source electrode coupled to the data line, and a drain electrode facing the source electrode, and a metal phosphorus oxide layer configured to cover the source electrode and the drain electrode.

公开(公告)号：US11961849B2

公开(公告)日：2024-04-16

申请号：US17342088

申请日：2021-06-08

Applicant: Samsung Display Co., LTD.

Inventor： Keum Hee Lee ,  Dong Hoon Shin ,  June Whan Choi ,  Seung Sok Son ,  Woo Geun Lee

IPC: H01L27/12

CPC classification number: H01L27/1248 ,  H01L27/124

Abstract: A display device includes a base layer; a first pattern disposed on the base layer; an insulating layer disposed on the first pattern and including layers; and a second pattern disposed on the insulating layer. At least two of the layers of the insulating layer include a same material.

公开(公告)号：US11626060B2

公开(公告)日：2023-04-11

申请号：US17478825

申请日：2021-09-17

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam Kim ,  Sung Hoon Lim ,  Woo Geun Lee ,  Kyu Sik Cho ,  Jae Beom Choi

IPC: G09G3/3266 ,  G09G3/20

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US11574970B2

公开(公告)日：2023-02-07

申请号：US16895756

申请日：2020-06-08

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Seul Ki Kim ,  Seung Sok Son ,  Kap Soo Yoon ,  Woo Geun Lee ,  Su Jung Jung ,  Seung Ha Choi

IPC: H01L27/32

Abstract: A display device includes a substrate having a display area and a pad area. A gate conductive layer disposed on the substrate includes a gate conductive metal layer and a gate capping layer. The gate conductive layer forms a gate electrode in the display area and a wire pad in the pad area that is exposed by a pad opening. An interlayer insulating film disposed on the gate conductive layer covers the gate electrode. A data conductive layer disposed on the interlayer insulating film in the display area includes source and drain electrodes. A passivation layer disposed on the data conductive layer covers the source and drain electrodes. A via layer is disposed on the passivation layer. A pixel electrode is disposed on the via layer. The pixel electrode is connected to the source electrode through a contact hole penetrating the via layer and the passivation layer.

公开(公告)号：US20220336669A1

公开(公告)日：2022-10-20

申请号：US17646973

申请日：2022-01-04

Applicant: SAMSUNG DISPLAY CO., LTD

Inventor： SEOK HWAN BANG ,  Hyun Seong Kang ,  Jong-in Kim ,  Joon Geol Kim ,  Seung Sok Son ,  Woo Geun Lee ,  Young Jae Jeon

IPC: H01L29/786 ,  H01L29/66

Abstract: A display device according to an embodiment includes: a substrate; a first conductive layer positioned on the substrate; a semiconductor layer positioned on the first conductive layer; a second conductive layer positioned on the semiconductor layer; an oxygen supply layer positioned under the second conductive layer, in contact with the second conductive layer, and having the same planar shape as the second conductive layer; and a light-emitting element connected to the second conductive layer, wherein the oxygen supply layer includes a metal oxide that includes one or more of indium, zinc, tin, or gallium, or alloys thereof.

公开(公告)号：US09524992B2

公开(公告)日：2016-12-20

申请号：US14875320

申请日：2015-10-05

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hye Young Ryu ,  Hee Jun Byeon ,  Woo Geun Lee ,  Kap Soo Yoon ,  Yoon Ho Kim ,  Chun Won Byun

IPC: G02F1/1362 ,  H01L27/12 ,  G02F1/1343 ,  G02F1/1368

CPC classification number: H01L27/127 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2001/136295 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262

Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.

公开(公告)号：US12279490B2

公开(公告)日：2025-04-15

申请号：US17465795

申请日：2021-09-02

Applicant: Samsung Display Co., Ltd.

Inventor： Woo Geun Lee ,  Young Jae Jeon ,  Woo Bin Lee ,  Jin Won Lee

IPC: H10K59/131

Abstract: A display device including a substrate; a signal line disposed on the substrate and to which a predetermined voltage signal is applied; a power auxiliary line to which a first source voltage is applied; a first driving voltage line to which a first driving voltage higher than the first source voltage is applied; and a first transistor disposed between the signal line and the first driving voltage line. The first transistor includes a first lower gate electrode connected to the power auxiliary line and a first upper gate electrode connected to the signal line.

公开(公告)号：US12002404B2

公开(公告)日：2024-06-04

申请号：US18132704

申请日：2023-04-10

Applicant: Samsung Display Co., Ltd.

Inventor： Kang Nam Kim ,  Sung Hoon Lim ,  Woo Geun Lee ,  Kyu Sik Cho ,  Jae Beom Choi

IPC: G09G3/20 ,  G09G3/3266 ,  G09G3/3233

CPC classification number: G09G3/2092 ,  G09G3/3233 ,  G09G3/3266 ,  G09G2310/0202 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0286 ,  G09G2310/08

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

公开(公告)号：US11980083B2

公开(公告)日：2024-05-07

申请号：US16832583

申请日：2020-03-27

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Keum Hee Lee ,  Joongeol Kim ,  Kap Soo Yoon ,  Woo Geun Lee ,  Seung-Ha Choi ,  Jiyun Hong

IPC: H01L51/56 ,  H10K71/00 ,  H10K71/20 ,  H10K71/60 ,  H10K102/10

CPC classification number: H10K71/00 ,  H10K71/233 ,  H10K71/60 ,  H10K2102/103

Abstract: A method of manufacturing a thin film transistor includes: forming an active pattern on a substrate; forming an insulating layer and a gate electrode layer on the active pattern in order; forming a photoresist pattern on the gate electrode layer; forming a preliminary gate electrode by wet etching the gate electrode layer using the photoresist pattern; forming an insulating pattern by dry etching the insulating layer using the photoresist pattern and the preliminary gate electrode; and forming a gate electrode by wet etching a side surface of the preliminary gate electrode using the photoresist pattern.