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公开(公告)号：US10998052B2
公开(公告)日：2021-05-04
申请号：US16996210
申请日：2020-08-18
发明人： Youn-Yeol Lee , Wook-Ghee Hahn
摘要： In a method of reading initialization information from a non-volatile memory device, when power-up is detected, the non-volatile memory device divides a source voltage to generate a low read pass voltage which is to be provided to unselected word lines in an initialization information read operation. The low read pass voltage is set as at least one voltage between a ground voltage and the source voltage. The non-volatile memory device allows the source voltage not to be pumped in the initialization information read operation, based on the power-up. In the initialization information read operation, the non-volatile memory device provides the low read pass voltage to the unselected word lines and provides a read voltage to a selected word line to read initialization information stored in the memory cells.
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公开(公告)号：US11631465B2
公开(公告)日：2023-04-18
申请号：US17495645
申请日：2021-10-06
发明人： Youn-Yeol Lee , Wook-Ghee Hahn
摘要： A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.
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公开(公告)号：US10770150B2
公开(公告)日：2020-09-08
申请号：US16181176
申请日：2018-11-05
发明人： Youn-Yeol Lee , Wook-Ghee Hahn
摘要： In a method of reading initialization information from a non-volatile memory device, when power-up is detected, the non-volatile memory device divides a source voltage to generate a low read pass voltage which is to be provided to unselected word lines in an initialization information read operation. The low read pass voltage is set as at least one voltage between a ground voltage and the source voltage. The non-volatile memory device allows the source voltage not to be pumped in the initialization information read operation, based on the power-up. In the initialization information read operation, the non-volatile memory device provides the low read pass voltage to the unselected word lines and provides a read voltage to a selected word line to read initialization information stored in the memory cells.
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公开(公告)号：US12033701B2
公开(公告)日：2024-07-09
申请号：US18123302
申请日：2023-03-19
发明人： Youn-Yeol Lee , Wook-Ghee Hahn
CPC分类号： G11C16/24 , G11C7/1039 , G11C16/0433 , G11C16/10 , G11C16/26
摘要： A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.
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公开(公告)号：US11164638B2
公开(公告)日：2021-11-02
申请号：US17014511
申请日：2020-09-08
发明人： Youn-Yeol Lee , Wook-Ghee Hahn
摘要： A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.
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公开(公告)号：US12073888B2
公开(公告)日：2024-08-27
申请号：US18123302
申请日：2023-03-19
发明人： Youn-Yeol Lee , Wook-Ghee Hahn
CPC分类号： G11C16/24 , G11C7/1039 , G11C16/0433 , G11C16/10 , G11C16/26
摘要： A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.
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公开(公告)号：US10790291B2
公开(公告)日：2020-09-29
申请号：US16241095
申请日：2019-01-07
发明人： Youn-Yeol Lee , Wook-Ghee Hahn
IPC分类号： G11C16/24 , H01L27/11524 , H01L27/11551 , H01L27/112 , G11C16/08 , G11C16/04 , G11C7/10 , G11C5/02
摘要： A non-volatile memory device includes an upper semiconductor layer vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group.
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公开(公告)号：US10056152B2
公开(公告)日：2018-08-21
申请号：US15493326
申请日：2017-04-21
发明人： Wook-Ghee Hahn , Ji-Sang Lee
CPC分类号： G11C16/3427 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C16/349 , G11C2211/563 , H01L27/11582
摘要： In a method of reading data in a nonvolatile memory device including a plurality of memory cells arranged at intersections of a plurality of word-lines and a plurality of bit-lines, a read request on a first word-line of the plurality of word-lines is received, a read operation is performed on a second word-line adjacent to the first word-line and a read operation is performed on the first word-line based on data read from memory cells of the second word-line. The read operation on the first word-line is performed by adjusting a level of recover read voltage applied to the first word-line during the read operation of the first word-line based on at least one of a program state of the data read from memory cells of the second word-line and an operating parameter of the nonvolatile memory device.
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公开(公告)号：US09818483B2
公开(公告)日：2017-11-14
申请号：US15263724
申请日：2016-09-13
发明人： Wook-Ghee Hahn , Chang-Yeon Yu
摘要： A row decoder of the semiconductor memory device includes a decoding and precharging unit that is connected between a high voltage node and a block word line, wherein the decoding and precharging unit precharges the block word line, and wherein the decoding and precharging unit includes one or more decoding transistors that decode an address and form a transmission path for transmitting a block selection voltage. The row decoder further includes a pass transistor block that transmits one or more row driving voltages to row lines in response to the block selection voltage, wherein the block selection voltage is boosted according to a switching operation of the pass transistor block.
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