Abstract:
A method for operating a memory device includes sensing a temperature of the resistive memory device, setting a level of a set voltage or current for writing to a memory cell based on the temperature, setting a level of a reset voltage for reset writing to the memory cell based on the temperature, and performing a write operation on the memory cell based on the level of the set voltage or current and the level of the reset voltage. The memory device may be a resistive memory device.
Abstract:
A method for operating a memory device includes sensing a change in temperature of the memory device, adjusting a level of a reference current for a read operation, and reading data from memory cells of the memory device based on the adjusted level of the reference current. The level of the reference current is adjusted from a reference value to a first value when the temperature of the memory device increases and is adjusted from the reference value to a second value when the temperature of the memory device decreases. A difference between the reference value and the first value is different from a difference the reference value and the second value.
Abstract:
A semiconductor apparatus includes a substrate, a first insulating layer on a logic region and a memory region of the substrate, a second insulating layer on the first insulating layer, a base insulating layer between the first insulating layer and second insulating layer over the logic region and the memory region, first interconnection structures passing the first insulating layer, second interconnection structures passing through the second insulating layer, a base interconnection structure passing through the base insulating layer over the logic region, and a variable resistance structure in the base insulating layer over the memory region. The variable resistance structure includes a lower electrode, a magnetoresistive device, and an upper electrode, which are sequentially stacked. The lower electrode and the upper electrode are electrically connected to one of the first interconnection structures and one of the second interconnection structures, respectively, over the memory region.