RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM, AND OPERATING METHOD THEREOF
    2.
    发明申请
    RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM, AND OPERATING METHOD THEREOF 有权
    电阻式存储器件,电阻式存储器系统及其操作方法

    公开(公告)号:US20160099049A1

    公开(公告)日:2016-04-07

    申请号:US14796131

    申请日:2015-07-10

    Abstract: A method for operating a memory device includes sensing a change in temperature of the memory device, adjusting a level of a reference current for a read operation, and reading data from memory cells of the memory device based on the adjusted level of the reference current. The level of the reference current is adjusted from a reference value to a first value when the temperature of the memory device increases and is adjusted from the reference value to a second value when the temperature of the memory device decreases. A difference between the reference value and the first value is different from a difference the reference value and the second value.

    Abstract translation: 用于操作存储器件的方法包括:检测存储器件的温度变化,调整读取操作的参考电流的电平,以及基于调节的参考电流的电平从存储器件的存储器单元读取数据。 当存储器件的温度升高时,将参考电流的电平从参考值调整到第一值,并且当存储器件的温度降低时,将参考电流的电平从参考值调整到第二值。 参考值和第一值之间的差异与参考值和第二值的差异不同。

    SEMICONDUCTOR APPARATUS INCLUDING MAGNETORESISTIVE DEVICE

    公开(公告)号:US20180211996A1

    公开(公告)日:2018-07-26

    申请号:US15925043

    申请日:2018-03-19

    CPC classification number: H01L27/228 H01L27/20 H01L27/222 H01L43/08 H01L43/10

    Abstract: A semiconductor apparatus includes a substrate, a first insulating layer on a logic region and a memory region of the substrate, a second insulating layer on the first insulating layer, a base insulating layer between the first insulating layer and second insulating layer over the logic region and the memory region, first interconnection structures passing the first insulating layer, second interconnection structures passing through the second insulating layer, a base interconnection structure passing through the base insulating layer over the logic region, and a variable resistance structure in the base insulating layer over the memory region. The variable resistance structure includes a lower electrode, a magnetoresistive device, and an upper electrode, which are sequentially stacked. The lower electrode and the upper electrode are electrically connected to one of the first interconnection structures and one of the second interconnection structures, respectively, over the memory region.

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