公开(公告)号：US11514991B1

公开(公告)日：2022-11-29

申请号：US17307285

申请日：2021-05-04

Applicant: SanDisk Technologies LLC

Inventor： Fanqi Wu ,  Hua-Ling Hsu ,  Deepanshu Dutta ,  Huai-yuan Tseng

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C29/50 ,  G11C16/26

Abstract: A method for detecting and isolating defective memory plane(s) of a non-volatile memory structure during a program verify operation, comprising: initiating, for each plane, a word line verify voltage level scan with a bit scan pass fail criterion and at a starting voltage located within an intended program threshold voltage distribution curve, incrementally decreasing the word line verify voltage by a predetermined offset until a specific condition of the scan is obtained, and storing the voltage at which the specific condition of the scan is obtained, wherein the stored voltage represents a voltage of an upper tail portion of an actual programmed threshold voltage distribution curve of the plane. The stored voltages of all of the memory planes of the structure are compared to determine which plane corresponds to the lowest stored voltage. A “fail” status is applied to the plane corresponding to the lowest stored voltage.

公开(公告)号：US11423996B1

公开(公告)日：2022-08-23

申请号：US17323293

申请日：2021-05-18

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Yi Song ,  Fanqi Wu

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines and arranged in strings. Each of the memory cells is also configured to retain a threshold voltage corresponding to one of a plurality of data states and be erased in an erase operation. A control circuit is coupled to the word lines and the strings and is configured to identify ones of the strings having a faster relative erase speed compared to others of the strings. During the erase operation, the control circuit raises the threshold voltage of the memory cells associated with the ones of the strings having the faster relative erase speed while not raising the threshold voltage of the memory cells associated with the others of the strings.

公开(公告)号：US20220310179A1

公开(公告)日：2022-09-29

申请号：US17212871

申请日：2021-03-25

Applicant: SanDisk Technologies LLC

Inventor： Fanqi Wu ,  Deepanshu Dutta ,  Huai-Yuan Tseng

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase pulse to a first grouping of non-volatile storage elements; after applying the first erase pulse, determining an upper tail of a threshold voltage distribution of the first grouping of non-volatile storage elements; determining a difference between the upper tail of the first grouping of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second grouping of non-volatile storage elements; and disabling, in a second erase loop of the plurality of erase loops, the erase operation on the first grouping of non-volatile storage elements if the difference is greater than or equal to the threshold amount.

公开(公告)号：US11437110B1

公开(公告)日：2022-09-06

申请号：US17212871

申请日：2021-03-25

Applicant: SanDisk Technologies LLC

Inventor： Fanqi Wu ,  Deepanshu Dutta ,  Huai-Yuan Tseng

IPC: G11C16/00 ,  G11C16/34 ,  G11C16/16 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11529

Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase pulse to a first grouping of non-volatile storage elements; after applying the first erase pulse, determining an upper tail of a threshold voltage distribution of the first grouping of non-volatile storage elements; determining a difference between the upper tail of the first grouping of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second grouping of non-volatile storage elements; and disabling, in a second erase loop of the plurality of erase loops, the erase operation on the first grouping of non-volatile storage elements if the difference is greater than or equal to the threshold amount.

公开(公告)号：US20230223084A1

公开(公告)日：2023-07-13

申请号：US17571124

申请日：2022-01-07

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Fanqi Wu ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26 ,  G11C7/10

CPC classification number: G11C16/102 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26 ,  G11C7/1048

Abstract: A memory device that uses different programming parameters base on the word line(s) to be programmed is described. The programming parameter PROGSRC_PCH provides a pre-charge voltage to physical word lines. In some instances, the PROGSRC_PCH voltage is decoupled, and a new PROGSRC_PCH represents an adjusted (e.g., increased) pre-charge voltage for a certain physical word line or word line zone (i.e., predetermined group of word lines). Using different PROGSRC_PCH voltages can limit or prevent Vt distribution window degradation, particularly for relatively low physical word lines. Additionally, the overall programming time and average current consumed can also be reduced.

公开(公告)号：US11972803B2

公开(公告)日：2024-04-30

申请号：US17571124

申请日：2022-01-07

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Fanqi Wu ,  Jiahui Yuan

IPC: G11C11/34 ,  G11C7/10 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/102 ,  G11C7/1048 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device that uses different programming parameters base on the word line(s) to be programmed is described. The programming parameter PROGSRC_PCH provides a pre-charge voltage to physical word lines. In some instances, the PROGSRC_PCH voltage is decoupled, and a new PROGSRC_PCH represents an adjusted (e.g., increased) pre-charge voltage for a certain physical word line or word line zone (i.e., predetermined group of word lines). Using different PROGSRC_PCH voltages can limit or prevent Vt distribution window degradation, particularly for relatively low physical word lines. Additionally, the overall programming time and average current consumed can also be reduced.

公开(公告)号：US11862249B2

公开(公告)日：2024-01-02

申请号：US17527747

申请日：2021-11-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiang Yang ,  Fanqi Wu ,  Jiacen Guo ,  Jiahui Yuan

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/34 ,  G11C16/24 ,  H10B43/27 ,  G11C11/56 ,  H01L25/065 ,  H10B43/10

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/3427 ,  H10B43/27 ,  G11C11/5671 ,  H01L25/0657 ,  H01L2225/06562 ,  H10B43/10

Abstract: In order to inhibit memory cells from programming and mitigate program disturb, the memory pre-charges channels of NAND strings connected to a common set of control lines by applying positive voltages to the control lines and applying voltages to a source line and bit lines connected to the NAND strings. The control lines include word lines and select lines. The word lines include an edge word line. The memory ramps down the positive voltages applied to the control lines, including ramping down control lines on a first side of the edge word line, ramping down the edge word line, and performing a staggered ramp down of three or more control lines on a second side of the edge word line. After the pre-charging, unselected NAND strings have their channel boosted to prevent programming and selected NAND strings experience programming on selected memory cells.

公开(公告)号：US20230154538A1

公开(公告)日：2023-05-18

申请号：US17527747

申请日：2021-11-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiang Yang ,  Fanqi Wu ,  Jiacen Guo ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11582 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  H01L27/11582 ,  G11C16/24 ,  G11C16/3427 ,  G11C11/5671

Abstract: In order to inhibit memory cells from programming and mitigate program disturb, the memory pre-charges channels of NAND strings connected to a common set of control lines by applying positive voltages to the control lines and applying voltages to a source line and bit lines connected to the NAND strings. The control lines include word lines and select lines. The word lines include an edge word line. The memory ramps down the positive voltages applied to the control lines, including ramping down control lines on a first side of the edge word line, ramping down the edge word line, and performing a staggered ramp down of three or more control lines on a second side of the edge word line. After the pre-charging, unselected NAND strings have their channel boosted to prevent programming and selected NAND strings experience programming on selected memory cells.

公开(公告)号：US20220359023A1

公开(公告)日：2022-11-10

申请号：US17307285

申请日：2021-05-04

Applicant: SanDisk Technologies LLC

Inventor： Fanqi Wu ,  Hua-Ling Hsu ,  Deepanshu Dutta ,  Huai-yuan Tseng

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C29/50

Abstract: A method for detecting and isolating defective memory plane(s) of a non-volatile memory structure during a program verify operation, comprising: initiating, for each plane, a word line verify voltage level scan with a bit scan pass fail criterion and at a starting voltage located within an intended program threshold voltage distribution curve, incrementally decreasing the word line verify voltage by a predetermined offset until a specific condition of the scan is obtained, and storing the voltage at which the specific condition of the scan is obtained, wherein the stored voltage represents a voltage of an upper tail portion of an actual programmed threshold voltage distribution curve of the plane. The stored voltages of all of the memory planes of the structure are compared to determine which plane corresponds to the lowest stored voltage. A “fail” status is applied to the plane corresponding to the lowest stored voltage.

公开(公告)号：US11355198B1

公开(公告)日：2022-06-07

申请号：US17152435

申请日：2021-01-19

Applicant: SanDisk Technologies LLC

Inventor： Fanqi Wu ,  Huai-Yuan Tseng ,  Sarath Puthenthermadam

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11556

Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase voltage pulse to a set of non-volatile storage elements; determining an upper tail of a threshold voltage distribution of the set of non-volatile storage elements after applying the first erase voltage pulse; determining a second erase voltage pulse based on the upper tail of the threshold voltage distribution of the set of non-volatile storage elements; and applying, in a second erase loop of the plurality of erase loops, the second erase voltage pulse to the set of non-volatile storage elements.