公开(公告)号：US10115735B2

公开(公告)日：2018-10-30

申请号：US15617499

申请日：2017-06-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitaka Amano ,  Kensuke Ishikawa ,  Shinya Inoue ,  Michiaki Sano

IPC: H01L29/06 ,  H01L27/11582 ,  H01L23/532 ,  H01L29/45 ,  H01L27/11556 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor device includes a silicon surface, a titanium silicide layer contacting the silicon surface, a first titanium nitride layer located over the titanium silicide layer, a titanium oxynitride layer contacting the first titanium nitride layer, a second titanium nitride layer contacting the titanium oxynitride layer, and a metal fill layer located over the second titanium nitride layer.

公开(公告)号：US12087626B2

公开(公告)日：2024-09-10

申请号：US17509323

申请日：2021-10-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitaka Amano ,  Kensuke Ishikawa

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L23/53238

Abstract: A method includes forming a semiconductor device, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure consisting essentially of an elemental metal that is not copper from a physically exposed conductive surface located at a bottom of the via portion of the integrated line-and-via cavity without filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that includes copper at an atomic percentage that is greater than 90% in the line portion of the integrated line-and-via cavity.

公开(公告)号：US20180247954A1

公开(公告)日：2018-08-30

申请号：US15617499

申请日：2017-06-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitaka Amano ,  Kensuke Ishikawa ,  Shinya Inoue ,  Michiaki Sano

IPC: H01L27/11582 ,  H01L23/532 ,  H01L29/45 ,  H01L27/11556 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L21/02186 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76889 ,  H01L23/5226 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/456 ,  H01L29/665

Abstract: A semiconductor device includes a silicon surface, a titanium silicide layer contacting the silicon surface, a first titanium nitride layer located over the titanium silicide layer, a titanium oxynitride layer contacting the first titanium nitride layer, a second titanium nitride layer contacting the titanium oxynitride layer, and a metal fill layer located over the second titanium nitride layer.

公开(公告)号：US11935784B2

公开(公告)日：2024-03-19

申请号：US17345315

申请日：2021-06-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitaka Amano ,  Yusuke Osawa ,  Kensuke Ishikawa ,  Mitsuteru Mushiga ,  Motoki Kawasaki ,  Shinsuke Yada ,  Masato Miyamoto ,  Syo Fukata ,  Takashi Kashimura ,  Shigehiro Fujino

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/535 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/76897 ,  H01L23/535 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer can be formed over an array region. Bit-line trenches are formed through the vertical layer stack. Bit-line-trench fill structures are formed in the bit-line trenches. Each of the bit-line-trench fill structures includes a stack of a bit line and a capping dielectric strip. At least one via-level dielectric layer can be formed over the vertical layer stack. A bit-line-contact via cavity can be formed through the at least one via-level dielectric layer and one of the capping dielectric strips. A bit-line-contact via structure formed in the bit-line-contact via cavity includes a stepped bottom surface including a top surface of one of the bit lines, a sidewall segment of the etch stop dielectric layer, and a segment of a top surface of the etch stop dielectric layer.