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    Methods, systems and computer readable media for submission queue pointer management
    2.
    发明授权
    Methods, systems and computer readable media for submission queue pointer management 有权

    公开(公告)号：US10235102B2

    公开(公告)日：2019-03-19

    申请号：US14929387

    申请日：2015-11-01

    Applicant: SanDisk Technologies LLC

    Inventor： Elkana Richter ,  Shay Benisty ,  Tal Sharifie

    IPC: G06F3/00 ,  G06F3/06 ,  G06F13/42

    Abstract: Methods, systems, and computer readable media for submission queue pointer management are disclosed. One method is implemented in a data storage device including a controller and a memory. The method includes fetching a plurality of commands from a submission queue. The method further includes parsing at least one of the commands. The method further includes, in response to successful parsing of at least one of the commands and prior to executing all of the commands, notifying a host to advance a head entry pointer for the submission queue by a number of entries corresponding to a number of the commands successfully parsed.

    Partial memory command fetching
    5.
    发明授权
    Partial memory command fetching 有权

    公开(公告)号：US09703716B2

    公开(公告)日：2017-07-11

    申请号：US14841094

    申请日：2015-08-31

    Applicant: SanDisk Technologies LLC

    Inventor： Amir Segev ,  Shay Benisty

    IPC: G06F12/08 ,  G06F12/0862 ,  G06F3/06

    CPC classification number: G06F12/0862 ,  G06F3/0613 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0688 ,  G06F13/10 ,  G06F2212/602

    Abstract: A system and method that allows idle process logic blocks in a memory device to be utilized when the idle process logic blocks would otherwise be remaining idle as the current memory commands are executed. Utilizing the otherwise idle process logic blocks in the memory device allows more optimized use of the process logic blocks while not slowing or otherwise interfering with the execution of the current memory commands. The otherwise idle process logic blocks can perform additional operations for subsequently fetched memory commands that may otherwise cause delays in execution of the subsequently fetched memory commands.

    MANAGED FETCHING AND EXECUTION OF COMMANDS FROM SUBMISSION QUEUES
    6.
    发明申请
    MANAGED FETCHING AND EXECUTION OF COMMANDS FROM SUBMISSION QUEUES 有权

    公开(公告)号：US20230004329A1

    公开(公告)日：2023-01-05

    申请号：US17940598

    申请日：2022-09-08

    Applicant: SanDisk Technologies LLC

    Inventor： Shay Benisty

    IPC: G06F3/06

    Abstract: The disclosure relates in some aspects to managing the fetching and execution of commands stored in submission queues. For example, execution of a command may be blocked at a data storage apparatus due to an internal blocking condition (e.g., a large number of commands of a particular type are pending for execution at the data storage device). As another example, execution of a command may be blocked at a data storage apparatus due to an external blocking condition (e.g., a host device may specify that certain commands are to be executed immediately one after another). The disclosure relates in some aspects to controlling how commands are fetched and executed so that commands that cannot be executed by the data storage apparatus in the near future do not prevent other commands (that are not subject to the same blocking condition) from being executed.

    Systems, Methods, and Computer-Readable Media for Managing Instruction Fetch in Virtual Computing Environments
    7.
    发明申请
    Systems, Methods, and Computer-Readable Media for Managing Instruction Fetch in Virtual Computing Environments 审中-公开

    公开(公告)号：US20180217951A1

    公开(公告)日：2018-08-02

    申请号：US15936364

    申请日：2018-03-26

    Applicant: SanDisk Technologies LLC

    Inventor： Shay Benisty ,  Rajesh Koul

    IPC: G06F13/16

    CPC classification number: G06F13/1642 ,  G06F2213/16 ,  G06F2213/24

    Abstract: Methods, systems, and computer readable media for intelligent fetching of storage device commands from submission queues are disclosed. The controller may implement a hierarchical scheme comprising first-level arbitration(s) between submission queues of each of a plurality of input/output virtualization (IOV) functions, and a second-level arbitration between the respective IOV functions. Alternatively, or in addition, the controller may implement a flat arbitration scheme, which may comprise selecting submission queue(s) from one or more groups, each group comprising submission queues of each of the plurality of IOV functions. In some embodiments, the controller implements a credit-based arbitration scheme. The arbitration scheme(s) may be modified in accordance with command statistics and/or current resource availability.

    METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR WRITE CLASSIFICATION AND AGGREGATION USING HOST MEMORY BUFFER (HMB)
    9.
    发明申请
    METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR WRITE CLASSIFICATION AND AGGREGATION USING HOST MEMORY BUFFER (HMB) 审中-公开

    公开(公告)号：US20180018101A1

    公开(公告)日：2018-01-18

    申请号：US15209739

    申请日：2016-07-13

    Applicant: SanDisk Technologies LLC

    Inventor： Shay Benisty ,  Tal Sharifie

    IPC: G06F3/06

    Abstract: A method for write aggregation using a host memory buffer includes fetching write commands and data specified by the write commands from a host over a bus to a non-volatile memory system coupled to the host. Writing the data specified by the write commands from the non-volatile memory system over the bus to the host. The method further includes aggregating the data specified by the write commands in a host memory buffer maintained in memory of the host. The method further includes determining whether the data in the host memory buffer has aggregated to a threshold amount. The method further includes, in response to determining that the data has aggregated to the threshold amount, reading the data from the host memory buffer to the non-volatile memory system and writing the data to non-volatile memory in the non-volatile memory system.

    Systems and methods for efficient power state transitions
    10.
    发明授权
    Systems and methods for efficient power state transitions 有权

    公开(公告)号：US10725677B2

    公开(公告)日：2020-07-28

    申请号：US15846592

    申请日：2017-12-19

    Applicant: SanDisk Technologies LLC

    Inventor： Noga Harari Shechter ,  Shay Benisty ,  Judah Gamliel Hahn ,  Yair Baram

    IPC: G06F3/00 ,  G06F3/06 ,  G06F13/42

    Abstract: A memory device may be configured to leverage memory resources of a host computing device to efficiently transition between different power states. In some embodiments, the memory device stores resume data within a host memory buffer (HMB) before transitioning to a low-power state, and uses the resume data stored within the HMB to resume operation from the low-power state. The memory device may be configured to pre-populate the HMB with resume data prior to transitioning to the low-power state. In some embodiments, the disclosed memory device is configured to gradually resume from the low-power state, which may comprise resuming services of the memory device in the order such services are required during the resume process.

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