公开(公告)号：US11282783B2

公开(公告)日：2022-03-22

申请号：US16809861

申请日：2020-03-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka Otsu ,  Masanori Terahara ,  Junpei Kanazawa

IPC: H01L23/52 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L29/66 ,  H01L27/11519 ,  H01L23/528 ,  H01L27/088 ,  H01L29/78 ,  H01L27/11524

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure vertically extending through the alternating stack, and an interconnection via structure laterally surrounded by the perforated dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers. The perforated dielectric moat structure includes a plurality of lateral openings at each level of the insulating layers, and does not include any opening at levels of the electrically conductive layers. An interconnection via structure can be laterally surrounded by the perforated dielectric moat structure, and can vertically extend through each insulating layer within the alternating stack.

公开(公告)号：US11114459B2

公开(公告)日：2021-09-07

申请号：US16675459

申请日：2019-11-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai ,  Hirofumi Tokita ,  Yoshitaka Otsu ,  Fumiaki Toyama ,  Yuki Mizutani

IPC: H01L27/00 ,  H01L29/00 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L29/788

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate, a first memory array region and a second memory array region that are laterally spaced apart along the first horizontal direction by an inter-array region therebetween, and memory stack structures extending through the alternating stacks in the first or second memory array region. Each of the alternating stacks includes a respective terrace region in which layers of a respective alternating stack have variable lateral extents within an area of the inter-array region, and a respective array interconnection region laterally offset from the respective terrace region and which continuously extends from the first memory array region to the second memory array region. Each of the alternating stacks has a width modulation along a second horizontal direction that is perpendicular to the first horizontal direction within the area of the inter-array region.

公开(公告)号：US10923498B2

公开(公告)日：2021-02-16

申请号：US16394233

申请日：2019-04-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka Otsu ,  Satoshi Shimizu ,  Makoto Koto

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556

Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory openings are formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer. A memory film is formally formed by a conformal deposition process, and a source contact layer is formed in the source cavity. Vertical semiconductor channels and drain regions are formed in remaining volumes of the memory openings on sidewalls of the source contact layer. A backside contact via structure is formed through the alternating stack and directly on a sidewall of the source contact layer.

公开(公告)号：US12068249B2

公开(公告)日：2024-08-20

申请号：US17516588

申请日：2021-11-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshiyuki Kuroko ,  Yoshitaka Otsu

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B43/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure including a dielectric fill material and vertically extending through the alternating stack. The perforated dielectric moat structure includes, at each level of the insulating layers, two rows of lengthwise dielectric pillar portions laterally extending along a first horizontal direction and two columns of widthwise dielectric pillar portions extending along a second horizontal directions that is perpendicular to the first horizontal direction. Each row of lengthwise dielectric pillar portions has a first center-to-center pitch. Each column of widthwise dielectric pillar portions has a second center-to-center pitch. A ratio of the second center-to-center pitch to the first center-to-center pitch is in a range from 1.50 to 2.0.

公开(公告)号：US11756877B2

公开(公告)日：2023-09-12

申请号：US17155512

申请日：2021-01-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuto Ohsawa ,  Kota Funayama ,  Hisaya Sakai ,  Yoshitaka Otsu

IPC: H01L23/52 ,  H01L23/522 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/5226 ,  H10B41/27 ,  H10B43/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a finned dielectric moat structure including a dielectric core portion vertically extending through each layer within the alternating stack and a vertical stack of dielectric fin portions laterally extending outward from the dielectric core portion, a vertical stack of insulating plates and dielectric material plates laterally surrounded by the finned dielectric moat structure, and an interconnection via structure vertically extending through the vertical stack and contacting a top surface of an underlying metal interconnect structure.

公开(公告)号：US11355515B2

公开(公告)日：2022-06-07

申请号：US16880365

申请日：2020-05-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naoto Hojo ,  Takahiro Tabira ,  Yoshitaka Otsu

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/768 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526

Abstract: Fabricating a three-dimensional memory device may include forming an alternating stack of insulating layers and sacrificial material layers over a substrate. Stepped surfaces are formed by patterning the alternating stack. Sacrificial pads are formed on physically exposed horizontal surfaces of the sacrificial material layers. A retro-stepped dielectric material portion is formed over the sacrificial pads. After memory stack structures extending through the alternating stack are formed, the sacrificial material layers and the sacrificial pads can be replaced with replacement material portions that include electrically conductive layers. The electrically conductive layers can be formed with thicker end portions. Contact via structures can be formed on the thicker end portions.

公开(公告)号：US10971514B2

公开(公告)日：2021-04-06

申请号：US16276996

申请日：2019-02-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka Otsu ,  Kei Nozawa ,  Yashushi Doda ,  Naoto Hojo ,  Yoshinobu Tanaka ,  Koichi Ito ,  Zhiwei Chen ,  Yusuke Ikawa ,  Takeshi Kawamura ,  Ryoichi Ehara

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L21/311 ,  H01L21/28 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526

Abstract: A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers. The dielectric support pillar structures may be formed before or after formation of stepped surfaces in the alternating stack.

公开(公告)号：US20200312859A1

公开(公告)日：2020-10-01

申请号：US16362988

申请日：2019-03-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka Otsu ,  Mitsuteru Mushiga ,  Yasushi Doda

IPC: H01L27/11521 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/065 ,  G11C5/06 ,  H01L21/8234 ,  H01L21/768

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate. Each alternating stack within the plurality of alternating stacks is laterally spaced apart from one another by a network of interconnected trenches that extend through each level of the insulating layers and the electrically conductive layers. Groups of memory stack structures extend through a respective one of the alternating stacks. The network of interconnected trenches includes first lengthwise trenches laterally extending along a first horizontal direction by a first lateral trench extension distance, second lengthwise trenches laterally extending along the first horizontal direction and interlaced with the first lengthwise trenches to provide a laterally alternating sequence, and widthwise trenches connecting an end of a respective one of the second lengthwise trenches to a portion of a sidewall of a first lengthwise trench. The staircase regions provide a compact layout.

公开(公告)号：US20200286916A1

公开(公告)日：2020-09-10

申请号：US16880365

申请日：2020-05-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naoto Hojo ,  Takahiro Tabira ,  Yoshitaka Otsu

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L21/768 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/28 ,  H01L27/1157

Abstract: Fabricating a three-dimensional memory device may include forming an alternating stack of insulating layers and sacrificial material layers over a substrate. Stepped surfaces are formed by patterning the alternating stack. Sacrificial pads are formed on physically exposed horizontal surfaces of the sacrificial material layers. A retro-stepped dielectric material portion is formed over the sacrificial pads. After memory stack structures extending through the alternating stack are formed, the sacrificial material layers and the sacrificial pads can be replaced with replacement material portions that include electrically conductive layers. The electrically conductive layers can be formed with thicker end portions. Contact via structures can be formed on the thicker end portions.

公开(公告)号：US10937801B2

公开(公告)日：2021-03-02

申请号：US16361773

申请日：2019-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka Otsu ,  Koichiro Nagata ,  Junpei Kanazawa

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and is patterned to form stepped surfaces. Memory stack structures are formed in a memory array region of the alternating stack. Support pillar structures are formed through the vertically alternating sequence within a staircase region. The support pillar structures are formed at lattice sites of a hexagonal lattice structure that includes unoccupied lattice sites. Portions of the continuous sacrificial material layers are replaced with electrically conductive layers. Contact via structures are formed on a respective one of the electrically conductive layers at the unoccupied lattice sites. Geometrical centers of the support pillar structures are arranged at vertices of a polygon having more than four vertices having a respective contact via structure located at a geometric center of the polygon in a plan view.