公开(公告)号：US20180331020A1

公开(公告)日：2018-11-15

申请号：US15594351

申请日：2017-05-12

Applicant: STMicroelectronics, Inc.

Inventor： Aaron CADAG ,  Ian Harvey ARELLANO ,  Ela Mia CADAG

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/49513 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/315 ,  H01L23/4952 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2221/68381 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/92247

Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.

公开(公告)号：US20210183750A1

公开(公告)日：2021-06-17

申请号：US17185742

申请日：2021-02-25

Applicant: STMicroelectronics, Inc.

Inventor： Rennier RODRIGUEZ ,  Aiza Marie AGUDON ,  Jefferson TALLEDO ,  Moonlord MANALO ,  Ela Mia CADAG ,  Rammil SEGUIDO

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.

公开(公告)号：US20240178006A1

公开(公告)日：2024-05-30

申请号：US18435915

申请日：2024-02-07

Applicant: STMICROELECTRONICS, INC.

Inventor： Ian Harvey ARELLANO ,  Aaron CADAG ,  Ela Mia CADAG

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L21/4821 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L21/561 ,  H01L21/565 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2224/92247

Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.

公开(公告)号：US20210313255A1

公开(公告)日：2021-10-07

申请号：US17353684

申请日：2021-06-21

Applicant: STMICROELECTRONICS, INC.

Inventor： Ian Harvey ARELLANO ,  Aaron CADAG ,  Ela Mia CADAG

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.

公开(公告)号：US20200343168A1

公开(公告)日：2020-10-29

申请号：US16848635

申请日：2020-04-14

Applicant: STMICROELECTRONICS, INC.

Inventor： Ela Mia CADAG ,  Frederick Ray GOMEZ ,  Aaron CADAG

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Generally described, one or more embodiments are directed to semiconductor packages comprising a plurality of leads and methods of forming same. The plurality of leads include active leads that are electrically coupled to bond pads of a semiconductor die and thereby coupled to active components of the semiconductor die, and inactive leads that are not electrically coupled to bond pads of the semiconductor die. The active leads have surfaces that are exposed at a lower surface of the semiconductor package and forms lands, while the inactive leads are not exposed at the lower surface of the package.

公开(公告)号：US20180358286A1

公开(公告)日：2018-12-13

申请号：US16107807

申请日：2018-08-21

Applicant: STMicroelectronics, Inc.

Inventor： Aaron CADAG ,  Ernesto ANTILANO, JR. ,  Ela Mia CADAG

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present disclosure is directed to a leadframe package having solder wettable sidewalls that is formed using a pre-molded leadframe and methods of manufacturing the same. A metal plated leadframe with a plurality of recesses and a plurality of apertures is placed into a top and bottom mold tool. A molding compound is then formed in the plurality of recesses and apertures in the leadframe to form a pre-molded leadframe. A plurality of die and wires are coupled to the pre-molded leadframe and the resulting combination is covered in an encapsulant. Alternatively, a bare leadframe can be processed and the metal layer can be applied after encapsulation. A saw or other cutting means is used for singulation to form leadframe packages. Each resulting leadframe package has a solder wettable sidewall for improving the strength of solder joints between the package and a circuit board.

公开(公告)号：US20220005857A1

公开(公告)日：2022-01-06

申请号：US17342765

申请日：2021-06-09

Applicant: STMicroelectronics, Inc.

Inventor： Aaron CADAG ,  Rohn Kenneth SERAPIO ,  Ela Mia CADAG

IPC: H01L27/146 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A first side of a tapeless leadframe package is etched to form a ring shaped protrusion and a lead protrusion extending from a base layer. An integrated circuit die is mounted to tapeless leadframe package in flip chip orientation with a front side facing the first side. An electrical and mechanical attachment is made between a bonding pad of the integrated circuit die and the lead protrusion. A mechanical attachment is made between the front side of the integrated circuit die and the ring shaped protrusion. The integrated circuit die and the protrusions from the tapeless leadframe package are encapsulated within an encapsulating block. The second side of the tapeless leadframe package is then etched to remove portions of the base layer and define a lead for a leadframe from the lead protrusion and further define a die support for the leadframe from the ring shaped protrusion.

公开(公告)号：US20190267311A1

公开(公告)日：2019-08-29

申请号：US16264822

申请日：2019-02-01

Applicant: STMicroelectronics, Inc.

Inventor： Ian Harvey ARELLANO ,  Aaron CADAG ,  Ela Mia CADAG

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.

公开(公告)号：US20170141014A1

公开(公告)日：2017-05-18

申请号：US14945291

申请日：2015-11-18

Applicant: STMICROELECTRONICS, INC.

Inventor： Ela Mia CADAG ,  Jefferson TALLEDO

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/4952 ,  H01L21/4828 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81002 ,  H01L2224/81986 ,  H01L2224/83002 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/83986 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2924/00

Abstract: One or more embodiments are directed to semiconductor packages having an integrated heatsink and methods of forming same. In one embodiment, a package includes a plurality of leads that support and enclose periphery portions of the semiconductor die. The leads have first and second, opposing surfaces that form outer surfaces of the package. The first surface of the leads may form a heatsink and the second surface of the leads form lands of the package for coupling to another device, substrate, or board. The package includes encapsulation material that surrounds the semiconductor die and located between upper portions of the leads. The package further includes a back filling material (or insulating material) that is below the semiconductor die and between lower portions of the leads.