Support structure for stacked integrated circuit dies
    1.
    发明授权
    Support structure for stacked integrated circuit dies 有权
    堆叠式集成电路管芯的支撑结构

    公开(公告)号:US09258890B2

    公开(公告)日:2016-02-09

    申请号:US14294875

    申请日:2014-06-03

    Abstract: Delamination of stacked integrated circuit die configurations on printed circuit boards is avoided by providing a metal trace support structure underneath the die stack. The metal trace support structure features substantially equally spaced thin metal traces in place of a contiguous metal plate which has been used in the past. Spaced apart thin metal traces are less vulnerable to thermal expansion than a metal plate which has a large thermal mass. The metal traces still provide structural stability, while preventing delamination of the die stack configuration during thermal processing. A method of attaching a bridge die stack configuration to a printed circuit board by adhering a die attach film to a field of metal traces is demonstrated. In addition, the electrical and structural integrity of the bridge die stack formed with a metal trace support structure is confirmed with test results.

    Abstract translation: 通过在管芯堆叠下方提供金属迹线支撑结构,可以避免印刷电路板上的堆叠集成电路管芯结构的分层。 金属迹线支撑结构具有基本相等间隔的细金属迹线,代替过去使用的连续金属板。 分隔开的薄金属迹线比具有大热质量的金属板不易受热膨胀。 金属迹线仍然提供结构稳定性,同时防止热处理期间芯片堆叠配置的分层。 证明了通过将管芯附着膜粘附到金属痕迹的领域将桥模组叠构造附着到印刷电路板的方法。 此外,用测试结果证实了由金属迹线支撑结构形成的桥模组的电气和结构完整性。

    Lead stabilization in semiconductor packages

    公开(公告)号:US12211774B2

    公开(公告)日:2025-01-28

    申请号:US16848635

    申请日:2020-04-14

    Abstract: Generally described, one or more embodiments are directed to semiconductor packages comprising a plurality of leads and methods of forming same. The plurality of leads include active leads that are electrically coupled to bond pads of a semiconductor die and thereby coupled to active components of the semiconductor die, and inactive leads that are not electrically coupled to bond pads of the semiconductor die. The active leads have surfaces that are exposed at a lower surface of the semiconductor package and forms lands, while the inactive leads are not exposed at the lower surface of the package.

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