公开(公告)号：US20160293450A1

公开(公告)日：2016-10-06

申请号：US14672664

申请日：2015-03-30

Applicant: STMICROELECTRONICS, INC.

Inventor： Godfrey DIMAYUGA ,  Jefferson Talledo

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device may include a multi-layer interconnect board having in stacked relation a lower conductive layer, a dielectric layer, and an upper conductive layer. The dielectric layer may have a recess formed with a bottom and sloping sidewall extending upwardly from the bottom. The upper conductive layer may include upper conductive traces extending across the sloping sidewall, and the lower conductive layer may include lower conductive traces. The semiconductor device may include vias extending between the lower and upper conductive layers, an IC carried by the multi-layer interconnect board in the recess, bond wires coupling upper conductive traces to the IC, and encapsulation material adjacent the IC and adjacent portions of the multi-layer interconnect board.

Abstract translation: 半导体器件可以包括具有下导电层，介电层和上导电层的堆叠关系的多层互连板。 电介质层可以具有形成有从底部向上延伸的底部和倾斜侧壁的凹部。 上导电层可以包括跨过倾斜侧壁延伸的上导电迹线，并且下导电层可以包括下导电迹线。 半导体器件可以包括在下导电层和上导电层之间延伸的通孔，由凹槽中的多层互连板承载的IC，将上导电迹线耦合到IC的接合线以及邻近IC的封装材料以及与IC的相邻部分 多层互连板。

公开(公告)号：US20170186698A1

公开(公告)日：2017-06-29

申请号：US14982018

申请日：2015-12-29

Applicant: STMICROELECTRONICS, INC.

Inventor： Godfrey DIMAYUGA ,  Frederick ARELLANO ,  Michael TABIERA

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48249 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/32245 ,  H01L2224/48247

Abstract: An electronic package includes a substrate having opposing first and second surfaces. Conductive areas are on a first surface of the substrate and include at least one edge conductive area. A plurality of conductive bumps are on the second surface of the substrate and coupled to respective ones of the conductive areas. An integrated circuit (IC) is carried by the substrate. Bond wires are coupled between the IC and respective ones of the conductive areas. An encapsulating material is over the IC and adjacent portions of the substrate. A conductive layer is on the encapsulating material, and at least one conductive body is coupled between the at least one edge conductive area and the conductive layer.